Patents by Inventor Aashish Sangoi

Aashish Sangoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11836035
    Abstract: A data storage device includes a non-volatile memory device including a memory block having a number of memory dies, and a controller coupled to the memory device. A memory access command is received and a memory access operation based on the received command is performed. A number of bytes transferred during the memory access operation is determined, and the determined number of bytes is analyzed to determine whether the number of transferred bytes is equal to a predetermined number. A transfer status fail bit is set if the number of transferred bytes is not equal to the predetermined number.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: December 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel Linnen, Aashish Sangoi, Kirubakaran Periyannan, Judah Gamliel Hahn
  • Patent number: 11782791
    Abstract: A data storage device includes a non-volatile memory device including a memory block having a number of arrays, a number of power regulators, and a controller coupled to the non-volatile memory device. The arrays include a number of memory devices. A first array is determined to be in a non-responsive condition and a power regulator supplying power to the first array is instructed to cycle power to the first array. After the power to the first array has been cycled, a determination is made as to whether the first array is in a responsive condition.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: October 10, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rohith Radhakrishnan, Alvin Capili Gomez, Aashish Sangoi
  • Publication number: 20230066185
    Abstract: A data storage device includes a non-volatile memory device including a memory block having a number of arrays, a number of power regulators, and a controller coupled to the non-volatile memory device. The arrays include a number of memory devices. A first array is determined to be in a non-responsive condition and a power regulator supplying power to the first array is instructed to cycle power to the first array. After the power to the first array has been cycled, a determination is made as to whether the first array is in a responsive condition.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 2, 2023
    Inventors: Rohith Radhakrishnan, Alvin Capili Gomez, Aashish Sangoi
  • Publication number: 20230039071
    Abstract: A data storage device includes a non-volatile memory device including a memory block having a number of memory dies, and a controller coupled to the memory device. A memory access command is received and a memory access operation based on the received command is performed. A number of bytes transferred during the memory access operation is determined, and the determined number of bytes is analyzed to determine whether the number of transferred bytes is equal to a predetermined number. A transfer status fail bit is set if the number of transferred bytes is not equal to the predetermined number.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 9, 2023
    Inventors: Daniel Linnen, Aashish Sangoi, Kirubakaran Periyannan, Judah Gamliel Hahn