Patents by Inventor Aashish Tripathi

Aashish Tripathi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250036848
    Abstract: A method for predicting voltage drop on a power delivery network of a 3D stacked device includes receiving a spatial power distribution map of a plurality of semiconductor dies of the 3D stacked device, receiving a spatial power source node location map for a plurality of power source nodes coupled to the 3D stacked device, dividing vertically the spatial power distribution map and the spatial power source node location map into overlapping windows, determining a voltage drop map in each of the windows based on the divided spatial power distribution map and the divided spatial power source node location map, and combining the voltage drop map in each of the windows to form a composite voltage drop map.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: XILINX, INC.
    Inventors: Aashish TRIPATHI, Sundeep Ram Gopal AGARWAL, Ashit DEBNATH, Atreyee SAHA, Praful JAIN
  • Publication number: 20240345977
    Abstract: A 3D device includes a first semiconductor chip and a second semiconductor chip stacked vertically. The first semiconductor chip includes a first plurality of tiles. The second semiconductor chip includes a second plurality of tiles. A bus electrically couples each of the first plurality of tiles to a corresponding one of the second plurality of tiles based on assignments of the first plurality of tiles and the second plurality of tiles to tile-to-tile pairs that define a minimized sum of bus delays among each possible tile-to-tile pairs. In each tile-to-tile pair, a net electrically couples each of a first plurality of pins to a corresponding one of a second plurality of pins based on assignments of the first plurality of pins to the second plurality of pins that define a minimized sum of net delays among each possible pin-to-pin pairs.
    Type: Application
    Filed: April 14, 2023
    Publication date: October 17, 2024
    Inventors: Dinesh D. GAITONDE, Aashish TRIPATHI, Ashit DEBNATH, Davis Boyd MOORE, Maithilee Rajendra KULKARNI, Abhishek Kumar JAIN
  • Patent number: 10990555
    Abstract: Embodiments herein describe an interface between PL fabric and a hardened block that includes a programmable pipeline. This pipeline includes at least a sequential element and a bypass path. For time critical nets in a netlist, the programmable IC routes a net through the sequential element. Doing so mitigates or eliminates the uncertainty associated with routing the net from the hardened block through PL fabric. Also, the sequential element can increase the available time for capturing the data. For less time critical nets, the net can route through the bypass path. This means the route from the hardened block to the PL fabric is determined on the fly by a routing algorithm rather than being fixed.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 27, 2021
    Assignee: XILINX, INC.
    Inventors: Aashish Tripathi, Sundeep Ram Gopal Agarwal
  • Patent number: 10503861
    Abstract: A netlist of a circuit design includes an interface portion and a main portion. The interface portion is decomposed into multiple levels. Each level specifies connections between a respective first set of circuit elements and a respective second set of circuit elements. The second set of circuit elements in each level, except a last level, includes the first set of circuit elements in a next level. The first set of circuit elements identified in a first level of the multiple levels have fixed locations. The second set of circuit elements in the multiple levels is placed-and-routed. The placing-and-routing of the second set of circuit elements in one level is completed before commencing placing-and-routing of the second set of circuit elements in the next level. The main portion is placed-and-routed after placing-and-routing the second set of circuit elements in the multiple levels.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: December 10, 2019
    Assignee: XILINX, INC.
    Inventors: Dinesh D. Gaitonde, Henri Fraisse, Sachin K. Bhutada, Aashish Tripathi, Ramakrishna K. Tanikella