Patents by Inventor AASHIT RAMACHANDRA KAMATH
AASHIT RAMACHANDRA KAMATH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9666688Abstract: A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.Type: GrantFiled: September 13, 2016Date of Patent: May 30, 2017Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Yisuo Li, Aashit Ramachandra Kamath, Zhixian Chen, Teng Soong Phua, Xinpeng Wang, Patrick Guo-Qiang Lo
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Publication number: 20160380080Abstract: A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.Type: ApplicationFiled: September 13, 2016Publication date: December 29, 2016Inventors: Fujio MASUOKA, Nozomu HARADA, Hiroki NAKAMURA, Yisuo LI, Aashit Ramachandra KAMATH, Zhixian CHEN, Teng Soong PHUA, Xinpeng WANG, Patrick Guo-Qiang LO
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Patent number: 9490362Abstract: A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.Type: GrantFiled: June 19, 2015Date of Patent: November 8, 2016Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Yisuo Li, Aashit Ramachandra Kamath, Zhixian Chen, Teng Soong Phua, Xinpeng Wang, Patrick Guo-Qiang Lo
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Publication number: 20150287822Abstract: A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.Type: ApplicationFiled: June 19, 2015Publication date: October 8, 2015Inventors: Fujio MASUOKA, Nozomu HARADA, Hiroki NAKAMURA, Yisuo LI, Aashit Ramachandra KAMATH, Zhixian CHEN, Teng Soong PHUA, Xinpeng WANG, Patrick Guo-Qiang LO
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Patent number: 9082838Abstract: In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line.Type: GrantFiled: September 25, 2013Date of Patent: July 14, 2015Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Navab Singh, Zhixian Chen, Aashit Ramachandra Kamath, Xinpeng Wang
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Patent number: 8836051Abstract: A method for producing a semiconductor device includes a first step including forming a planar silicon layer and forming first and second pillar-shaped silicon layers; a second step including forming a gate insulating film around each of the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, the thickness of the polysilicon film being smaller than half of a distance between the first and second pillar-shaped silicon layers, forming a third resist, and forming a gate line; and a third step including depositing a fourth resist so that a portion of the polysilicon film on an upper side wall of each of the first and second pillar-shaped silicon layers is exposed, removing the exposed portion of the polysilicon film, removing the fourth resist, and removing the metal film to form first and second gate electrodes.Type: GrantFiled: June 3, 2013Date of Patent: September 16, 2014Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Xiang Li, Xinpeng Wang, Zhixian Chen, Aashit Ramachandra Kamath, Navab Singh
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Publication number: 20140091372Abstract: In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line.Type: ApplicationFiled: September 25, 2013Publication date: April 3, 2014Applicant: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: FUJIO MASUOKA, NOZOMU HARADA, HIROKI NAKAMURA, NAVAB SINGH, ZHIXIAN CHEN, AASHIT RAMACHANDRA KAMATH, XINPENG WANG
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Publication number: 20130328138Abstract: A method for producing a semiconductor device includes a first step including forming a planar silicon layer and forming first and second pillar-shaped silicon layers; a second step including forming a gate insulating film around each of the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, the thickness of the polysilicon film being smaller than half of a distance between the first and second pillar-shaped silicon layers, forming a third resist, and forming a gate line; and a third step including depositing a fourth resist so that a portion of the polysilicon film on an upper side wall of each of the first and second pillar-shaped silicon layers is exposed, removing the exposed portion of the polysilicon film, removing the fourth resist, and removing the metal film to form first and second gate electrodes.Type: ApplicationFiled: June 3, 2013Publication date: December 12, 2013Inventors: FUJIO MASUOKA, NOZOMU HARADA, HIROKI NAKAMURA, XIANG LI, XINPENG WANG, ZHIXIAN CHEN, AASHIT RAMACHANDRA KAMATH, NAVAB SINGH