Patents by Inventor Aastha Uppal
Aastha Uppal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250112106Abstract: An integrated circuit (IC) device includes a device substrate with front- and backside IC dies and an integrated heat spreader over the backside die. The heat spreader and the backside die may be coupled to the backside of the device substrate within an array of contacts. The backside heat spreader may include a mask layer over a thermally conductive layer. The IC device may include or be coupled to second substrate (such as a motherboard). The backside heat spreader may be thermally coupled to a heat spreader or heat sink by vias through the second substrate. The backside heat spreader may enclose the backside IC die in an electrically conductive cage.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Tarek Gebrael, Darshan Ravoori, Matthew Magnavita, Aastha Uppal, Xiao Lu
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Patent number: 12048123Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device comprising a main body portion and a resilient portion extending from the main body portion, wherein the resilient portion has a plurality of extensions, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a stiffener attached to the electronic substrate, wherein at least a portion of the plurality of extensions of the resilient portion of the heat dissipation device are biased against the stiffener.Type: GrantFiled: January 23, 2020Date of Patent: July 23, 2024Assignee: Intel CorporationInventors: Aastha Uppal, Je-Young Chang, Ravindranath Mahajan
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Patent number: 12021016Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.Type: GrantFiled: June 10, 2020Date of Patent: June 25, 2024Assignee: Intel CorporationInventors: Chandra Mohan Jha, Pooya Tadayon, Aastha Uppal, Weihua Tang, Paul Diglio, Xavier Brun
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Patent number: 11830783Abstract: Embodiments include semiconductor packages. A semiconductor package include a high-power electronic component and an embedded heat spreader (EHS) in a package substrate. The EHS is adjacent to the high-power electronic component. The semiconductor package includes a plurality of thermal interconnects below the EHS and the package substrate, and a plurality of dies on the package substrate. The thermal interconnects is coupled to the EHS. The EHS is below the high-power electronic component and embedded within the package substrate. The high-power electronic component has a bottom surface substantially proximate to a top surface of the EHS. The EHS is a copper heat sink, and the high-power electronic component is an air core inductor or a voltage regulator. The thermal interconnects are comprised of thermal ball grid array balls or thermal adhesive materials. The thermal interconnects couple a bottom surface of the package substrate to a top surface of a substrate.Type: GrantFiled: October 11, 2019Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Aastha Uppal, Divya Mani, Je-Young Chang
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Patent number: 11769753Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.Type: GrantFiled: July 31, 2018Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: George Vakanas, Aastha Uppal, Shereen Elhalawaty, Aaron McCann, Edvin Cetegen, Tannaz Harirchian, Saikumar Jayaraman
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Patent number: 11735495Abstract: Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. Fluid conduits may be at least partially defined by an interconnect trace comprising a metal. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly.Type: GrantFiled: February 27, 2019Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Omkar Karhade, Mitul Modi, Edvin Cetegen, Aastha Uppal
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Patent number: 11721607Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a metal foam surrounding the at least one integrated circuit device and contacting the thermal interface material. The integrated circuit assembly may further include a stiffener attached to the electronic substrate and surrounding the at least one integrated circuit device, wherein the metal foam is disposed between the stiffener, the at least one integrated circuit device, the electronic substrate, and the heat dissipation device.Type: GrantFiled: January 23, 2020Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Aastha Uppal, Je-Young Chang
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Patent number: 11676883Abstract: An Integrated Circuit (IC) assembly, comprising an IC package coupled to a substrate, and a subassembly comprising a thermal interface layer. The thermal interface layer comprises a phase change material (PCM) over the IC package. At least one thermoelectric cooling (TEC) apparatus is thermally coupled to the thermal interface layer.Type: GrantFiled: March 15, 2019Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Javed Shaikh, Je-Young Chang, Kelly Lofgreen, Weihua Tang, Aastha Uppal
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Patent number: 11664294Abstract: An integrated circuit assembly may be formed using a phase change material as an electromagnetic shield and as a heat dissipation mechanism for the integrated circuit assembly. In one embodiment, the integrated circuit assembly may comprise an integrated circuit package including a first substrate having a first surface and an opposing second surface, and at least one integrated circuit device having a first surface and an opposing second surface, wherein the at least one integrated circuit device is electrically attached by the first surface thereof to the first surface of the first substrate; and a phase change material formed on the integrated circuit package.Type: GrantFiled: January 7, 2019Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Aastha Uppal, Je-Young Chang, Weihua Tang, Minseok Ha
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Patent number: 11574851Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.Type: GrantFiled: February 27, 2019Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Aastha Uppal, Omkar Karhade, Ram Viswanath, Je-Young Chang, Weihua Tang, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh
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Patent number: 11545407Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.Type: GrantFiled: January 10, 2019Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, Jr.
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Patent number: 11387175Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.Type: GrantFiled: August 9, 2018Date of Patent: July 12, 2022Assignee: Intel CorporationInventors: Debendra Mallik, Sanka Ganesan, Pilin Liu, Shawna Liff, Sri Chaitra Chavali, Sandeep Gaan, Jimin Yao, Aastha Uppal
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Publication number: 20210391244Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.Type: ApplicationFiled: June 10, 2020Publication date: December 16, 2021Inventors: Chandra Mohan JHA, Pooya TADAYON, Aastha UPPAL, Weihua TANG, Paul DIGLIO, Xavier BRUN
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Publication number: 20210259134Abstract: Embodiments disclosed herein include an integrated heat spreader (IHS). In an embodiment, the IHS comprises a main body, where the main body comprises a first surface and a second surface opposite from the second surface. In an embodiment, the IHS further and a support extending from the first surface of the main body. In an embodiment, the support comprises a shell, and a layer over an interior surface of the shell.Type: ApplicationFiled: February 19, 2020Publication date: August 19, 2021Inventors: Aastha UPPAL, Divya MANI, Je-Young CHANG
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Publication number: 20210249326Abstract: An integrated circuit assembly may be formed comprising at least one integrated circuit device, a heat dissipation device having a thermal contact surface with at least one containment structure extending into or from the heat dissipation device at the thermal contact surface, and a thermal interface material between the at least one integrated circuit device and the heat dissipation device, wherein the thermal interface material contacts the at least one containment structure of the heat dissipation device.Type: ApplicationFiled: February 12, 2020Publication date: August 12, 2021Applicant: Intel CorporationInventors: Aastha Uppal, Je-Young Chang
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Publication number: 20210233832Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a metal foam surrounding the at least one integrated circuit device and contacting the thermal interface material. The integrated circuit assembly may further include a stiffener attached to the electronic substrate and surrounding the at least one integrated circuit device, wherein the metal foam is disposed between the stiffener, the at least one integrated circuit device, the electronic substrate, and the heat dissipation device.Type: ApplicationFiled: January 23, 2020Publication date: July 29, 2021Applicant: INTEL CORPORATIONInventors: Aastha Uppal, Je-Young Chang
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Publication number: 20210235596Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device comprising a main body portion and a resilient portion extending from the main body portion, wherein the resilient portion has a plurality of extensions, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a stiffener attached to the electronic substrate, wherein at least a portion of the plurality of extensions of the resilient portion of the heat dissipation device are biased against the stiffener.Type: ApplicationFiled: January 23, 2020Publication date: July 29, 2021Applicant: Intel CorporationInventors: Aastha Uppal, Je-Young Chang, Ravindranath Mahajan
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Publication number: 20210111091Abstract: Embodiments include semiconductor packages. A semiconductor package include a high-power electronic component and an embedded heat spreader (EHS) in a package substrate. The EHS is adjacent to the high-power electronic component. The semiconductor package includes a plurality of thermal interconnects below the EHS and the package substrate, and a plurality of dies on the package substrate. The thermal interconnects is coupled to the EHS. The EHS is below the high-power electronic component and embedded within the package substrate. The high-power electronic component has a bottom surface substantially proximate to a top surface of the EHS. The EHS is a copper heat sink, and the high-power electronic component is an air core inductor or a voltage regulator. The thermal interconnects are comprised of thermal ball grid array balls or thermal adhesive materials. The thermal interconnects couple a bottom surface of the package substrate to a top surface of a substrate.Type: ApplicationFiled: October 11, 2019Publication date: April 15, 2021Inventors: Aastha UPPAL, Divya MANI, Je-Young CHANG
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Publication number: 20200294884Abstract: An Integrated Circuit (IC) assembly, comprising an IC package coupled to a substrate, and a subassembly comprising a thermal interface layer. The thermal interface layer comprises a phase change material (PCM) over the IC package. At least one thermoelectric cooling (TEC) apparatus is thermally coupled to the thermal interface layer.Type: ApplicationFiled: March 15, 2019Publication date: September 17, 2020Applicant: Intel CorporationInventors: Javed Shaikh, Je-Young Chang, Kelly Lofgreen, Weihua Tang, Aastha Uppal
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Publication number: 20200273775Abstract: Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly.Type: ApplicationFiled: February 27, 2019Publication date: August 27, 2020Inventors: Omkar Karhade, Mitul Modi, Edvin Cetegen, Aastha Uppal