Patents by Inventor Aastha Uppal

Aastha Uppal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11830783
    Abstract: Embodiments include semiconductor packages. A semiconductor package include a high-power electronic component and an embedded heat spreader (EHS) in a package substrate. The EHS is adjacent to the high-power electronic component. The semiconductor package includes a plurality of thermal interconnects below the EHS and the package substrate, and a plurality of dies on the package substrate. The thermal interconnects is coupled to the EHS. The EHS is below the high-power electronic component and embedded within the package substrate. The high-power electronic component has a bottom surface substantially proximate to a top surface of the EHS. The EHS is a copper heat sink, and the high-power electronic component is an air core inductor or a voltage regulator. The thermal interconnects are comprised of thermal ball grid array balls or thermal adhesive materials. The thermal interconnects couple a bottom surface of the package substrate to a top surface of a substrate.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Aastha Uppal, Divya Mani, Je-Young Chang
  • Patent number: 11769753
    Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: September 26, 2023
    Assignee: Intel Corporation
    Inventors: George Vakanas, Aastha Uppal, Shereen Elhalawaty, Aaron McCann, Edvin Cetegen, Tannaz Harirchian, Saikumar Jayaraman
  • Patent number: 11735495
    Abstract: Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. Fluid conduits may be at least partially defined by an interconnect trace comprising a metal. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Mitul Modi, Edvin Cetegen, Aastha Uppal
  • Patent number: 11721607
    Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a metal foam surrounding the at least one integrated circuit device and contacting the thermal interface material. The integrated circuit assembly may further include a stiffener attached to the electronic substrate and surrounding the at least one integrated circuit device, wherein the metal foam is disposed between the stiffener, the at least one integrated circuit device, the electronic substrate, and the heat dissipation device.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Aastha Uppal, Je-Young Chang
  • Patent number: 11676883
    Abstract: An Integrated Circuit (IC) assembly, comprising an IC package coupled to a substrate, and a subassembly comprising a thermal interface layer. The thermal interface layer comprises a phase change material (PCM) over the IC package. At least one thermoelectric cooling (TEC) apparatus is thermally coupled to the thermal interface layer.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: June 13, 2023
    Assignee: Intel Corporation
    Inventors: Javed Shaikh, Je-Young Chang, Kelly Lofgreen, Weihua Tang, Aastha Uppal
  • Patent number: 11664294
    Abstract: An integrated circuit assembly may be formed using a phase change material as an electromagnetic shield and as a heat dissipation mechanism for the integrated circuit assembly. In one embodiment, the integrated circuit assembly may comprise an integrated circuit package including a first substrate having a first surface and an opposing second surface, and at least one integrated circuit device having a first surface and an opposing second surface, wherein the at least one integrated circuit device is electrically attached by the first surface thereof to the first surface of the first substrate; and a phase change material formed on the integrated circuit package.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: May 30, 2023
    Assignee: Intel Corporation
    Inventors: Aastha Uppal, Je-Young Chang, Weihua Tang, Minseok Ha
  • Patent number: 11574851
    Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Aastha Uppal, Omkar Karhade, Ram Viswanath, Je-Young Chang, Weihua Tang, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh
  • Patent number: 11545407
    Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, Jr.
  • Patent number: 11387175
    Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Sanka Ganesan, Pilin Liu, Shawna Liff, Sri Chaitra Chavali, Sandeep Gaan, Jimin Yao, Aastha Uppal
  • Publication number: 20210391244
    Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 16, 2021
    Inventors: Chandra Mohan JHA, Pooya TADAYON, Aastha UPPAL, Weihua TANG, Paul DIGLIO, Xavier BRUN
  • Publication number: 20210259134
    Abstract: Embodiments disclosed herein include an integrated heat spreader (IHS). In an embodiment, the IHS comprises a main body, where the main body comprises a first surface and a second surface opposite from the second surface. In an embodiment, the IHS further and a support extending from the first surface of the main body. In an embodiment, the support comprises a shell, and a layer over an interior surface of the shell.
    Type: Application
    Filed: February 19, 2020
    Publication date: August 19, 2021
    Inventors: Aastha UPPAL, Divya MANI, Je-Young CHANG
  • Publication number: 20210249326
    Abstract: An integrated circuit assembly may be formed comprising at least one integrated circuit device, a heat dissipation device having a thermal contact surface with at least one containment structure extending into or from the heat dissipation device at the thermal contact surface, and a thermal interface material between the at least one integrated circuit device and the heat dissipation device, wherein the thermal interface material contacts the at least one containment structure of the heat dissipation device.
    Type: Application
    Filed: February 12, 2020
    Publication date: August 12, 2021
    Applicant: Intel Corporation
    Inventors: Aastha Uppal, Je-Young Chang
  • Publication number: 20210233832
    Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a metal foam surrounding the at least one integrated circuit device and contacting the thermal interface material. The integrated circuit assembly may further include a stiffener attached to the electronic substrate and surrounding the at least one integrated circuit device, wherein the metal foam is disposed between the stiffener, the at least one integrated circuit device, the electronic substrate, and the heat dissipation device.
    Type: Application
    Filed: January 23, 2020
    Publication date: July 29, 2021
    Applicant: INTEL CORPORATION
    Inventors: Aastha Uppal, Je-Young Chang
  • Publication number: 20210235596
    Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device comprising a main body portion and a resilient portion extending from the main body portion, wherein the resilient portion has a plurality of extensions, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a stiffener attached to the electronic substrate, wherein at least a portion of the plurality of extensions of the resilient portion of the heat dissipation device are biased against the stiffener.
    Type: Application
    Filed: January 23, 2020
    Publication date: July 29, 2021
    Applicant: Intel Corporation
    Inventors: Aastha Uppal, Je-Young Chang, Ravindranath Mahajan
  • Publication number: 20210111091
    Abstract: Embodiments include semiconductor packages. A semiconductor package include a high-power electronic component and an embedded heat spreader (EHS) in a package substrate. The EHS is adjacent to the high-power electronic component. The semiconductor package includes a plurality of thermal interconnects below the EHS and the package substrate, and a plurality of dies on the package substrate. The thermal interconnects is coupled to the EHS. The EHS is below the high-power electronic component and embedded within the package substrate. The high-power electronic component has a bottom surface substantially proximate to a top surface of the EHS. The EHS is a copper heat sink, and the high-power electronic component is an air core inductor or a voltage regulator. The thermal interconnects are comprised of thermal ball grid array balls or thermal adhesive materials. The thermal interconnects couple a bottom surface of the package substrate to a top surface of a substrate.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 15, 2021
    Inventors: Aastha UPPAL, Divya MANI, Je-Young CHANG
  • Publication number: 20200294884
    Abstract: An Integrated Circuit (IC) assembly, comprising an IC package coupled to a substrate, and a subassembly comprising a thermal interface layer. The thermal interface layer comprises a phase change material (PCM) over the IC package. At least one thermoelectric cooling (TEC) apparatus is thermally coupled to the thermal interface layer.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Javed Shaikh, Je-Young Chang, Kelly Lofgreen, Weihua Tang, Aastha Uppal
  • Publication number: 20200273775
    Abstract: Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Inventors: Omkar Karhade, Mitul Modi, Edvin Cetegen, Aastha Uppal
  • Publication number: 20200273772
    Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Aastha Uppal, Omkar Karhade, Ram Viswanath, Je-Young Chang, Weihua Tang, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh
  • Publication number: 20200273768
    Abstract: IC packages including a heat spreading material comprising crystalline carbon. The heat spreading material may be applied directly to an IC die surface, for example at a die prep stage, prior to an application or build-up of packaging material, so that the high thermal conductivity may best mitigate any hot spots that develop at the IC die surface during operation. The heat spreading material may be applied to surface of the IC die.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh
  • Publication number: 20200273811
    Abstract: IC package including a material preform comprising graphite. The material preform may have a thermal conductivity higher than that of other materials in the package and may therefore mitigate the formation of hot spots within an IC die during device operation. The preform may have high electrical conductivity suitable for EMI shielding. The preform may comprise a graphite sheet that can be adhered to a package assembly with an electrically conductive adhesive, applied, for example over an IC die surface and a surrounding package dielectric material. Electrical interconnects of the package may be coupled to the graphite sheet as an EMI shield. The package preform may be grounded to a reference potential through electrical interconnects of the package, which may be further coupled to a system-level ground plane. System-level thermal solutions may interface with the package-level graphite sheet.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Debendra Mallik, Mitul Modi, Sanka Ganesan, Edvin Cetegen, Omkar Karhade, Ravindranath Mahajan, James C. Matayabas, Jr., Jan Krajniak, Kumar Singh, Aastha Uppal