Abstract: An immersion cooling server system with AI accelerator apparatuses using in-memory compute chiplet devices. This system includes one or more immersion tanks with heat transfer fluid and configured with at least a condenser device. A plurality of AI accelerator servers is immersed in the heat transfer fluid in a bottom portion of the tanks and is configured to process transformer workloads while cooled by the immersion cooling configuration. Each of the servers includes a plurality of multiprocessors each having at least a first server central processing unit (CPU) and a second server CPU, both of which are coupled to a plurality of switch devices. Each switch device is coupled to a plurality of AI accelerator apparatuses. The apparatus includes one or more chiplets, each of which includes a plurality of digital in-memory compute (DIMC) devices configured to perform high throughput matrix computations for transformer based models.

Abstract: Sparsity-aware reconfiguration compute-in-memory (CIM) static random access memory (SRAM) systems are disclosed. In one aspect, a reconfigurable precision succession approximation register (SAR) analog-to-digital converter (ADC) that has the ability to form (n+m) bit precision using n-bit and m-bit sub-ADCs is provided. By controlling which sub-ADCs are used based on data sparsity, precision may be maintained as needed while providing a more energy efficient design.

Abstract: A server system with AI accelerator apparatuses using in-memory compute chiplet devices. The system includes a plurality of multiprocessors each having at least a first server central processing unit (CPU) and a second server CPU, both of which are coupled to a plurality of switch devices. Each switch device is coupled to a plurality of AI accelerator apparatuses. The apparatus includes one or more chiplets, each of which includes a plurality of tiles. Each tile includes a plurality of slices, a CPU, and a hardware dispatch device. Each slice can include a digital in-memory compute (DIMC) device configured to perform high throughput computations. In particular, the DIMC device can be configured to accelerate the computations of attention functions for transformer-based models (a.k.a. transformers) applied to machine learning applications. A single input multiple data (SIMD) device configured to further process the DIMC output and compute softmax functions for the attention functions.

Abstract: Sparsity-aware reconfiguration compute-in-memory (CIM) static random access memory (SRAM) systems are disclosed. In one aspect, a reconfigurable precision succession approximation register (SAR) analog-to-digital converter (ADC) that has the ability to form (n+m) bit precision using n-bit and m-bit sub-ADCs is provided. By controlling which sub-ADCs are used based on data sparsity, precision may be maintained as needed while providing a more energy efficient design.

Abstract: A texture filtering unit and a method are disclosed that provide multiple variants of an approximate trilinear filtering operation. A texture sampling and filtering unit may be configured to determine a level-of-detail (LOD) value for a sample point in texture space, and select, based on the LOD value, a fine mip-level and a coarse mip-level from the mip-map. The closer of the two selected mip-levels to the sample point is determined, and farther of the two selected mip-levels from the sample point is determined. A first quad of texels in the closer mip-level and a second quad of texels in the farther mip-level are then determined. A total of five or fewer texels are selected from the first quad of texels and from the second quad of texels. A filtered value for the sample point is determined based on an approximate trilinear filtering operation on the selected texels.

Abstract: A texture filtering unit and a method are disclosed that provide multiple variants of an approximate trilinear filtering operation. A texture sampling and filtering unit may be configured to determine a level-of-detail (LOD) value for a sample point in texture space, and select, based on the LOD value, a fine mip-level and a coarse mip-level from the mip-map. The closer of the two selected mip-levels to the sample point is determined, and farther of the two selected mip-levels from the sample point is determined. A first quad of texels in the closer mip-level and a second quad of texels in the farther mip-level are then determined. A total of five or fewer texels are selected from the first quad of texels and from the second quad of texels. A filtered value for the sample point is determined based on an approximate trilinear filtering operation on the selected texels.