Patents by Inventor Abbas Ismail Attarwala

Abbas Ismail Attarwala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7575955
    Abstract: A process for fabricating an electronic package for a Thermally Enhanced BGA package including the steps of fabricating a thermally conductive support member, an adhesive bonding member, and a circuitized member; sandwiching the members together, forming a cavity therein; bonding adhesively the members together with heat and pressure; bonding adhesively a chip to the support member within the cavity; and connecting electrically the chip to the circuitized member. A process for fabricating an electronic flip chip package, including the steps of fabricating an adhesive bonding member, a flip chip, and a circuitized member; aligning the members with respect to each other; sandwiching the members together; bonding the members together with heat and pressure; and connecting electrically the flip chip to the circuitized member.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: August 18, 2009
    Assignee: Ismat Corporation
    Inventor: Abbas Ismail Attarwala
  • Patent number: 7105931
    Abstract: An electronic package substrate for an electronic package that includes an adhesive bonding member having two planar surfaces and an orifice there through for receiving a chip and a circuitized member having two planar surfaces, one surface being bonded to one of the planar surfaces of the bonding member, the circuitized member being electrically connectable to the chip. The electronic package substrate is fabricated for an electronic package for either a wire bonded chip, a tab bonded chip, or a flip chip.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: September 12, 2006
    Inventor: Abbas Ismail Attarwala
  • Publication number: 20040195701
    Abstract: An electronic package substrate for an electronic package that includes an adhesive bonding member having two planar surfaces and an orifice there through for receiving a chip and a circuitized member having two planar surfaces, one surface being bonded to one of the planar surfaces of the bonding member, said circuitized member being electrically connectable to the chip. An electronic package for a wire bonded chip or tab bonded chip that includes an adhesive bonding member having two planar surfaces and an orifice there through; a circuitized member bonded to one of the planar surfaces and having an orifice there through overlying the orifice in the bonding member; a support member bonded to the other planar surface, blocking the orifices, thereby forming a cavity; and a chip bonded within the cavity to the support member and electrically connected to the circuitized member.
    Type: Application
    Filed: January 6, 2004
    Publication date: October 7, 2004
    Inventor: Abbas Ismail Attarwala