Patents by Inventor Abbas Morshed
Abbas Morshed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111704Abstract: Embodiments herein describe a NoC where its internal switches have buffers with pods that can be assigned to different virtual channels. A subset of the pods in a buffer can be grouped together to form a VC. In this manner, different pod groups in a buffer can be assigned to different VCs (or to different types of NoC data units), where VCs that transmit wider data units can be assigned more pods than VCs that transmit narrower data units.Type: ApplicationFiled: October 4, 2022Publication date: April 4, 2024Inventors: Krishnan SRINIVASAN, Abbas MORSHED, Sagheer AHMAD
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Publication number: 20240045822Abstract: Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC inter-chip bridge (NICB) circuitry that interfaces between the NoC and the off-chip device over C2C interconnections. The NICB circuitry may be configurable in a full mode to map packetized memory-mapped traffic to the C2C interconnections in a 1:1 fashion and in a compressed to map packetized memory-mapped traffic to the C2C interconnections in a less-than 1:1 fashion.Type: ApplicationFiled: August 2, 2022Publication date: February 8, 2024Inventors: Krishnan SRINIVASAN, Ygal ARBEL, Sagheer AHMAD, Abbas MORSHED
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Patent number: 11832035Abstract: Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.Type: GrantFiled: April 16, 2021Date of Patent: November 28, 2023Assignee: XILINX, INC.Inventors: Aman Gupta, Sagheer Ahmad, Ygal Arbel, Abbas Morshed, Eun Mi Kim
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Patent number: 11714779Abstract: Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.Type: GrantFiled: March 25, 2020Date of Patent: August 1, 2023Assignee: XILINX, INC.Inventors: Abbas Morshed, Ygal Arbel, Eun Mi Kim
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Publication number: 20230036531Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.Type: ApplicationFiled: July 29, 2021Publication date: February 2, 2023Applicant: XILINX, INC.Inventors: Krishnan SRINIVASAN, Shishir KUMAR, Sagheer AHMAD, Abbas MORSHED, Aman GUPTA
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Publication number: 20220337923Abstract: Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.Type: ApplicationFiled: April 16, 2021Publication date: October 20, 2022Inventors: Aman GUPTA, Sagheer AHMAD, Ygal ARBEL, Abbas MORSHED, Eun Mi KIM
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Publication number: 20210303508Abstract: Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.Type: ApplicationFiled: March 25, 2020Publication date: September 30, 2021Inventors: Abbas MORSHED, Ygal ARBEL, Eun Mi KIM
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Patent number: 11010322Abstract: A network on a chip (NOC) peripheral interface (NPI) includes an NPI root, a plurality of switches coupled to the NPI root, and a plurality of NPI protocol blocks coupled to the plurality of switches. The NPI root, the plurality of switches, and the plurality of NPI protocol blocks are configured to route signals received from a master to a plurality of circuit blocks. A non-service command is routed to an intended circuit block of the plurality of circuit blocks. A switch of the plurality of switches or an NPI protocol block of the plurality of NPI protocol blocks generate a response message for a service command query with the destination address associated with the intended circuit block that is received from the master instead of routing the service command query to the intended circuit block.Type: GrantFiled: June 21, 2019Date of Patent: May 18, 2021Assignee: XILINX, INC.Inventor: Abbas Morshed
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Patent number: 9940241Abstract: A system is provided comprising: a packet routing network; Flash storage circuitry; a management processor coupled as an endpoint to the network; an input/output (I/O) circuit coupled as an endpoint to the network; a packet processing circuit coupled as an endpoint to the network; a cache storage circuit coupled to send and received packets to and from the packet processing circuit; and a RAID management circuit coupled as an endpoint to the network and configured to send and receive packets to and from the Flash storage circuitry; wherein the management processor is configured to determine routing of packets among the I/O circuit, packet processing circuit and RAID management circuit; and wherein the packet processing circuit is configured to control cache read requests, cache write requests and cache data eviction.Type: GrantFiled: November 24, 2014Date of Patent: April 10, 2018Assignee: Sanmina CorporationInventors: Sharad Mehrotra, Jon Livesey, Thomas Gourley, Abbas Morshed
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Patent number: 9715428Abstract: A system comprises a first host device, a second host device, and first and second cache controllers. A cache controller includes a cache memory interface, a first peripheral interface that communicates with the first host device, a second peripheral interface that communicates with the second host device, logic circuitry that loads a cache command from a cache command memory of the first host device, loads a cache command from a cache command memory of the second cache controller, and performs the cache commands, and error checking circuitry that detects an uncorrectable error in a first cache controller/memory pair and indicates the uncorrectable error condition to at least one of the first and second host devices. At least one of the first host device or the second host device writes contents of the cache memory of the second cache controller/memory pair to a main memory in response to the indication.Type: GrantFiled: November 24, 2014Date of Patent: July 25, 2017Assignee: Sanmina CorporationInventors: Abbas Morshed, Chuan-Wen George Tsang, Christopher Youngworth
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Patent number: 9672180Abstract: A system comprises a first cache controller and at least a second cache controller. The first cache controller and the second cache controller each include a cache memory interface, an inter-cache controller communication link configured for bidirectional communication with the other cache controller, a first peripheral interface, a second peripheral interface, and logic circuitry. The first peripheral interface communicates with a first host device and the second peripheral interface communicates with a second host device. The first host device and the second host device are each connected to the first and second cache controllers by the first and second peripheral interfaces. The logic circuitry loads a cache command from a cache command memory of the first host device, loads a cache command from a cache command memory of the second cache controller, and performs the cache commands.Type: GrantFiled: November 24, 2014Date of Patent: June 6, 2017Assignee: Sanmina CorporationInventors: Abbas Morshed, Jon Livesey, Sharad Mehrotra
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Patent number: 9608936Abstract: A system is provided comprising: a packet routing network; Flash storage circuitry; a management processor coupled as an endpoint to the network; an input/output (I/O) circuit coupled as an endpoint to the network; a packet processing circuit coupled as an endpoint to the network; and a RAID management circuit coupled as an endpoint to the network and configured to send and receive packets to and from the Flash storage circuitry; wherein the management processor is configured to determine routing of packets among the I/O circuit, packet processing circuit and RAID management circuit.Type: GrantFiled: November 24, 2014Date of Patent: March 28, 2017Assignee: Sanmina CorporationInventors: Sharad Mehrotra, Thomas Gourley, Abbas Morshed, Julian Ratcliffe, Jon Livesey
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Patent number: 9413694Abstract: A system and method are disclosed for processing a packet. Processing the packet comprises receiving the packet; translating the packet from a first protocol-specific format to a canonical packet format; translating the packet from the canonical packet format to a second protocol-specific format; and forwarding the packet.Type: GrantFiled: August 25, 2015Date of Patent: August 9, 2016Assignee: Brixham Solutions Ltd.Inventors: Fong Liaw, Jan Medved, Abbas Morshed, Yijun Xiong, John Z. Yu
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Patent number: 9384147Abstract: A system comprises a host device and a cache controller. The host device includes a command buffer and a host application that posts a cache command that includes a cache key and a key aging alias in the command buffer. The cache controller includes logic circuitry configured to load the cache command from the command buffer of the first host device into the buffer memory, identify a match, if any, for the cache key in the command queue, perform the cache command, and return cache completion status information to the first host application, wherein the cache completion status information includes a value of the key aging alias in cache metadata when a match for the cache key is found and includes a value of the key aging alias provided by the first host application when a match for the cache key is not found.Type: GrantFiled: November 24, 2014Date of Patent: July 5, 2016Assignee: Saratoga Speed, Inc.Inventors: Abbas Morshed, Chuan-Wen George Tsang, Christopher Youngworth
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Publication number: 20150365356Abstract: A system and method are disclosed for processing a packet. Processing the packet comprises receiving the packet; translating the packet from a first protocol-specific format to a canonical packet format; translating the packet from the canonical packet format to a second protocol-specific format; and forwarding the packet.Type: ApplicationFiled: August 25, 2015Publication date: December 17, 2015Inventors: Fong Liaw, Jan Medved, Abbas Morshed, Yijun Xiong, John Z. Yu
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Patent number: 9143463Abstract: A system and method are disclosed for processing a packet. Processing the packet comprises receiving the packet; translating the packet from a first protocol-specific format to a canonical packet format; translating the packet from the canonical packet format to a second protocol-specific format; and forwarding the packet.Type: GrantFiled: June 18, 2014Date of Patent: September 22, 2015Assignee: BRIXHAM SOLUTIONS LTD.Inventors: Fong Liaw, Jan Medved, Abbas Morshed, Yijun Xiong, John Z. Yu
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Patent number: 8861545Abstract: A system and method are disclosed for processing a packet. Processing the packet comprises receiving the packet; translating the packet from a first protocol-specific format to a canonical packet format; translating the packet from the canonical packet format to a second protocol-specific format; and forwarding the packet.Type: GrantFiled: May 27, 2011Date of Patent: October 14, 2014Assignee: Brixham Solutions Ltd.Inventors: Fong Liaw, Jan Medved, Abbas Morshed, Yijun Xiong, John Z. Yu
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Publication number: 20140301407Abstract: A system and method are disclosed for processing a packet. Processing the packet comprises receiving the packet; translating the packet from a first protocol-specific format to a canonical packet format; translating the packet from the canonical packet format to a second protocol-specific format; and forwarding the packet.Type: ApplicationFiled: June 18, 2014Publication date: October 9, 2014Inventors: Fong Liaw, Jan Medved, Abbas Morshed, Yijun Xiong, John Z. Yu
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Patent number: 8286027Abstract: An I/O device includes a host interface that may receive and process transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may determine, as each packet is received, whether each transaction packet has an error and to store information corresponding to any detected errors. The error handling unit may include an error processor that may be configured to execute error processing instructions to determine any error processing operations based upon the information. The error processor may also generate and send one or more instruction operations, each corresponding to a particular error processing operation. The error handling unit may also include an error processing unit that may execute the one or more instruction operations to perform the particular error processing operations.Type: GrantFiled: May 25, 2010Date of Patent: October 9, 2012Assignee: Oracle International CorporationInventors: John E. Watkins, Elisa Rodrigues, Abbas Morshed
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Publication number: 20110296256Abstract: An I/O device includes a host interface that may receive and process transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may determine, as each packet is received, whether each transaction packet has an error and to store information corresponding to any detected errors. The error handling unit may include an error processor that may be configured to execute error processing instructions to determine any error processing operations based upon the information. The error processor may also generate and send one or more instruction operations, each corresponding to a particular error processing operation. The error handling unit may also include an error processing unit that may execute the one or more instruction operations to perform the particular error processing operations.Type: ApplicationFiled: May 25, 2010Publication date: December 1, 2011Inventors: John E. Watkins, Elisa Rodrigues, Abbas Morshed