Patents by Inventor Abbas Rashid
Abbas Rashid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160036696Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.Type: ApplicationFiled: October 6, 2015Publication date: February 4, 2016Applicant: Broadcom CorporationInventors: David T. HASS, Abbas RASHID
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Patent number: 9154443Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.Type: GrantFiled: October 20, 2009Date of Patent: October 6, 2015Assignee: Broadcom CorporationInventors: David T Hass, Abbas Rashid
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Patent number: 9088474Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.Type: GrantFiled: August 31, 2004Date of Patent: July 21, 2015Assignee: Broadcom CorporationInventors: Abbas Rashid, David T. Hass
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Patent number: 9083628Abstract: A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.Type: GrantFiled: February 4, 2013Date of Patent: July 14, 2015Assignee: Juniper Networks, Inc.Inventors: Mark Bryers, Elango Ganesan, Frederick Gruner, David Hass, Robert Hathaway, Ramesh Panwar, Ricardo Ramirez, Abbas Rashid, Mark Vilas, Nazar Zaidi, Yen Lee, Chau Anh Ngoc Nguyen, John Phillips, Yuhong Zhou, Gregory G. Spurrier, Sankar Ramanoorthi, Michael Freed
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Patent number: 9069564Abstract: A method and system are provided for performing efficient and effective scheduling in a multi-threaded system. Dynamic control of scheduling is provided, in which priority weights can be assigned for some or all of the threads in the multi-threaded system. The priority weights are employed to control prioritization of threads and thread instructions by a scheduler. An instruction count for each thread is used in combination with the priority weights to determine the prioritization order in which instructions are fetched and assigned to execution units for processing.Type: GrantFiled: February 14, 2012Date of Patent: June 30, 2015Assignee: NETLOGIC MICROSYSTEMS, INC.Inventors: Abbas Rashid, David T. Hass
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Patent number: 8370528Abstract: A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.Type: GrantFiled: July 26, 2010Date of Patent: February 5, 2013Assignee: Juniper Networks, Inc.Inventors: Mark Bryers, Elango Ganesan, Frederick Gruner, David Hass, Robert Hathaway, Ramesh Panwar, Ricardo Ramirez, Abbas Rashid, Mark Vilas, Yen Lee, John Phillips, Yuhong Andy Zhou, Gregory G. Spurrier, Sankar Ramanoorthi, Michael Freed
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Publication number: 20110255542Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.Type: ApplicationFiled: April 11, 2011Publication date: October 20, 2011Inventors: David T. HASS, Abbas RASHID
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Publication number: 20110225398Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.Type: ApplicationFiled: May 24, 2011Publication date: September 15, 2011Inventors: David T. Hass, Abbas Rashid
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Patent number: 7984268Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.Type: GrantFiled: July 23, 2004Date of Patent: July 19, 2011Assignee: NetLogic Microsystems, Inc.Inventors: David T. Hass, Abbas Rashid
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Patent number: 7924828Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.Type: GrantFiled: August 31, 2004Date of Patent: April 12, 2011Assignee: NetLogic Microsystems, Inc.Inventors: David T. Hass, Abbas Rashid
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Publication number: 20110019550Abstract: A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.Type: ApplicationFiled: July 26, 2010Publication date: January 27, 2011Applicant: Juniper Networks, Inc.Inventors: Mark Bryers, Elango Ganesan, Frederick Gruner, David Hass, Robert Hathaway, Ramesh Panwar, Ricardo Ramirez, Abbas Rashid, Mark Vilas, Nazar Zaidi, Yen Lee, Chau Anh Ngoc Nguyen, John Phillips, Yuhong Andy Zhou, Gregory S. Spurrier, Sankar Ramanoorthi, Michael Freed
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Patent number: 7813364Abstract: A cross-bar switch includes a set of input ports to accept data packets and a set of sink ports in communication with the input ports to forward the data packets. Each sink port includes a communications link interface with a Retry input. When a signal is asserted on the Retry input, the sink port aborts transmission of a data packet and waits a predetermined period of time to retransmit the data packet.Type: GrantFiled: December 11, 2006Date of Patent: October 12, 2010Assignee: Juniper Networks, Inc.Inventors: Abbas Rashid, Nazar Zaidi, Mark Bryers, Fred Gruner
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Patent number: 7808503Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.Type: GrantFiled: December 19, 2006Date of Patent: October 5, 2010Assignee: Apple Inc.Inventors: Jerome F. Duluk, Jr., Richard E. Hessel, Vaughn T. Arnold, Jack Benkual, Joseph P. Bratt, George Cuan, Stephen L. Dodgen, Emerson S. Fang, Zhaoyu Gong, Thomas Y. Yo, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N. Papakipos, Jason R. Redgrave, Sushma S. Trivedi, Nathan D. Tuck, Shun Wai Go, Lindy Fung, Tuan D. Nguyen, Joseph P. Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan-Wei Tsay
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Patent number: 7765328Abstract: A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.Type: GrantFiled: November 7, 2007Date of Patent: July 27, 2010Assignee: Juniper Networks, Inc.Inventors: Mark Bryers, Elango Ganesan, Frederick Gruner, David Hass, Robert Hathaway, Ramesh Panwar, Ricardo Ramirez, Abbas Rashid, Mark Vilas, Nazar Zaidi, Yen Lee, Chau Ahn Ngoc Nguyen, John Phillips, Yuhong Andy Zhou, Gregory G. Spurrier, Sankar Ramanoorthi, Michael Freed
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Patent number: 7733905Abstract: A cross-bar switch includes a set of input ports for receiving data packets and a set of sink ports for transmitting the received packets to identified targets. A set of data rings couples the input ports to the sink ports. Each sink port utilizes the set of data rings to simultaneously accept multiple data packets targeted to the same destination—creating a non-blocking cross-bar switch. Sink ports are also each capable of supporting multiple targets—providing the cross-bar switch with implicit multicast capability.Type: GrantFiled: February 1, 2007Date of Patent: June 8, 2010Assignee: Juniper Networks, Inc.Inventors: Abbas Rashid, Nazar Zaidi, Mark Bryers, Fred Gruner
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Publication number: 20100042785Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.Type: ApplicationFiled: October 20, 2009Publication date: February 18, 2010Inventors: David T. Hass, Abbas Rashid
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Patent number: 7627717Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.Type: GrantFiled: December 20, 2007Date of Patent: December 1, 2009Assignee: RMI CorporationInventors: David T. Hass, Abbas Rashid
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Patent number: 7467243Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.Type: GrantFiled: August 31, 2004Date of Patent: December 16, 2008Assignee: RMI CorporationInventors: Abbas Rashid, David T. Hass
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Publication number: 20080126709Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.Type: ApplicationFiled: December 20, 2007Publication date: May 29, 2008Inventors: David T. Hass, Abbas Rashid
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Publication number: 20080114887Abstract: A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.Type: ApplicationFiled: November 7, 2007Publication date: May 15, 2008Applicant: Juniper Networks, Inc.Inventors: Mark Bryers, Elango Ganesan, Frederick Gruner, David Hass, Robert Hathaway, Ramesh Panwar, Ricardo Ramirez, Abbas Rashid, Mark Vilas, Nazar Zaidi, Yen Lee, Chau Nguyen, John Phillips, Yuhong Zhou, Gregory Spurrier, Sankar Ramanoorthi, Michael Freed