Abstract: A memory system and method for storing data in one or more storage chips includes: one or more memory cards each having a plurality of storage chips, and each chip having a plurality of dies having a plurality of memory cells; a memory controller comprising a translation module, the translation module further comprising: a logical to virtual translation table (LVT) having a plurality of entries, each entry in the LVT configured to map a logical address to a virtual block address (VBA), where the VBA corresponds to a group of the memory cells on the one or more memory cards, wherein each entry in the LVT further includes a write wear level count to track the number of writing operations to the VBA, and a read wear level count to track the number of read operations for the VBA mapped to that LVT entry.

Abstract: A memory system and method for storing data in one or more storage chips includes: one or more memory cards each having a plurality of storage chips, and each chip having a plurality of dies having a plurality of memory cells; a memory controller comprising a translation module, the translation module further comprising: a logical to virtual translation table (LVT) having a plurality of entries, each entry in the LVT configured to map a logical address to a virtual block address (VBA), where the VBA corresponds to a group of the memory cells on the one or more memory cards, wherein each entry in the LVT further includes a write wear level count to track the number of writing operations to the VBA, and a read wear level count to track the number of read operations for the VBA mapped to that LVT entry.

Abstract: A memory system and method for storing data in one or more storage chips includes: one or more memory cards each having a plurality of storage chips, and each chip having a plurality of dies having a plurality of memory cells; a memory controller comprising a translation module, the translation module further comprising: a logical to virtual translation table (LVT) having a plurality of entries, each entry in the LVT configured to map a logical address to a virtual block address (VBA), where the VBA corresponds to a group of the memory cells on the one or more memory cards, wherein each entry in the LVT further includes a write wear level count to track the number of writing operations to the VBA, and a read wear level count to track the number of read operations for the VBA mapped to that LVT entry.

Abstract: A computer-implemented method (and associated computing system and computer program product) comprises distributing computing workloads among a plurality of processing units of a computing system. The method further comprises, responsive to detecting a reduced power supply capacity of the computing system: determining, based on historical workload information, a first workload of the computing workloads to prioritize the completion thereof, and prioritizing power delivery to a first processing unit of the plurality of processing units to which the first workload is distributed. The method further comprises powering down the first processing unit responsive to completion of the first workload.

Abstract: A computer-implemented method (and associated computing system and computer program product) comprises distributing computing workloads among a plurality of processing units of a computing system. The method further comprises, responsive to detecting a reduced power supply capacity of the computing system: determining, based on historical workload information, a first workload of the computing workloads to prioritize the completion thereof, and prioritizing power delivery to a first processing unit of the plurality of processing units to which the first workload is distributed. The method further comprises powering down the first processing unit responsive to completion of the first workload.