Abstract: A variable attenuator for electronically controlling dual beam intensity comprising a laser source for emitting a light beam, a twisted nematic liquid crystal for exposure control of the light beam, a double-sided multi-layer dielectric thin film coated polarization plate for decreasing the s-component of the light beam to less than or equal to 0.0001 of the light beam emitted from the laser source, and a beam splitting crystal for separating said light beam into two beams of equal intensity.

Abstract: A multiple diode laser array used in a ROS scanning system is modified to reduce the effects of undesirable spatial exposure variation at the surface of certain type of layered, semi-transparent photoreceptors. The spatial absorption variation is later manifested as a "plywooding" pattern formed on output prints derived from the exposed photoreceptor. The laser array is modified to form a merged scanning beam at the photoreceptor surface of two or more diode outputs, each output operating at a different wavelength than the other. In one embodiment, a plurality of diodes, each at a different wavelength, are sequentially addressed, and an image of each diode is scanned across the photoreceptor which results in an exposure distribution that would be similar to that formed by an incoherent beam.

Abstract: This invention relates to an electro-optic modulator device, such as a multi-gate light valve for an electro-optic line printer, wherein the different elements are uniquely combined in a package utilizing VLSI principles. A specially designed integrated circuit package is utilized to enable the bonding of one or two electro-optical devices as a single unit. As each electro-optical device has its chip pads at one end of the device, special modifications need to be made to joint the pads to the external connectors. The electro-optical crystal, which may be mounted on a glass plate, is bonded to the integrated circuit chip. Sonic bonding or the two layer metal technique may be used for the crystal to chip bonding.

Abstract: A high density charge coupled device imaging array 88 with a bilinear array of photosites on a single integrated circuit chip is utilized in an image scanning configuration. Offset photosites 90a, 94a in the two separated rows are coupled via transfer gates 98, 106 to storage registers 104, 108 and then to two shift registers 110, 112, and via transfer gates 96 directly to two shift registers 100, 102 in a quadrilinear array. The output of these four shift registers 110,102,110,112 are multiplexed to generate a single output pulse train representative of the information scanned. By separating the offset rows 90, 94 of photosites by a row 92 therebetween, the necessity for accurate alignment of the photosite areas is reduced.

Abstract: A high resolution quadrilinear CCD imager array which incorporates a unique on-chip multiplexing technique. The multiplexing is accomplished in two consecutive steps. First the two video outputs on either side of the sensor array are multiplexed through a CCD channel. This multiplexed output is then sensed through a source follower circuit, one on either side of said sensor array. A non-overlapping clocking technique is used to sample and hold the signals on either side and simultaneously the second level of multiplexing is also accomplished, giving a 4:1 video multiplexed output. The final signal is sensed through a second stage source follower circuit. Bad pixel deletion is effected by overriding the sample and hold signal.

Abstract: A barrier gate isolated channel charge coupled device integrated circuit imager which permits the barrier gate to define the transfer channel from an inner shift register to an outer shift register to the exclusion of the field oxide layer. By extending the length of the barrier gate slightly and bringing the storage gate down and out around each barrier gate, and widening the field oxide dimension, relative to one another, the buried channel potential voltage remains high allowing for more efficient charge transfer or, if desired, the isolated channel dimension can be decreased while still maintaining a high minimum buried channel potential voltage.

Abstract: A high density charge coupled device imaging array 58 with a bilinear array 60, 62 of photosites on a single integrated circuit chip is utilized in an image scanning configuration. Offset photosites 60a, 62a in two rows are coupled via transfer gates 64 to storage register 72 and then to two shift registers 74, 76, and via transfer gates 66 directly to two shift registers 68, 70 in a quadrilinear array. The output of these four shift registers 68, 70, 74, 76 are multiplexed to generate a single output pulse train representative of the information scanned.