Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.

Abstract: An electronic device comprises a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material; a stiffening layer including one of a ceramic or glass, the stiffening layer including a first surface contacting a first surface of the first RDL and including a through layer via (TLV); and multiple integrated circuit (ICs) arranged on a second surface of the first RDL and including bonding pads, wherein the conductive traces of the first RDL provide electrical continuity between at least one bonding pad of the ICs and at least one TLV of the stiffening layer.

Abstract: A device may include a carrier with a plurality of first bump pads. The device may include a first die with a plurality of second bump pads. The device may include a plurality of first bumps disposed between the plurality of first bump pads and the plurality of second bump pads to electrically connect the first die to the carrier. The device may include solder disposed between the plurality of first bump pads and the plurality of second bump pads, wherein the plurality of first bump pads have a first pitch relative to one another, and the plurality of second bump pads have a second pitch relative to one another, and wherein the first pitch is different from the second pitch. Each first bump pad of the plurality of first bump pads is larger than each second bump pad of the plurality of second bump pads.

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for forming a package that includes a mold compound on a first surface of a redistribution layer, where the mold compound includes one or more cavities, and wherein one or more dies are placed within the cavities. In embodiments, one or more dies may be placed on the second surface of the redistribution layer. In embodiments, the dies, mold compound, and redistribution layer may have different coefficients of thermal expansion, in order to reduce warpage of the package during manufacture and operation. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein relate to systems, apparatuses, or processes for packages that include substrates that include one or more die in a cavity within the substrate, where sides and a bottom of the cavity are lined with a heat spreader, or TIM, material that is thermally coupled to a side of the substrate using thermally conductive vias. In embodiments, thermally conductive vias may be thermally coupled with the heat spreader at the side of the substrate. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein relate to systems, apparatuses, or processes for forming a die that has active circuitry within the die and also one or more vias that extend through the die that are electrically isolated from the active circuitry. In embodiments, the active circuitry may be within a region within a die, for example in the center of the die, and the vias may be in an extended area around the active circuitry of the die. In embodiments, an existing die may be provided, and an extended area may be formed on the existing die into which the vias may be placed. Other embodiments may be described and/or claimed.

Abstract: An electronic system has a printed circuit board and a substrate. The substrate has two sides, a top and bottom. At least one memory unit is connected to the bottom side of the substrate and at least one processor is connected to the top side of the substrate. The memory is connected to the processor with interconnects that pass through the substrate.

Abstract: An electronic device comprises a substrate including an organic material; a glass bridge die included in the substrate, the glass bridge die including electrically conductive interconnect; and a first integrated circuit (IC) die and at least a second IC die arranged on a surface of the substrate and including bonding pads connected to the interconnect of the glass bridge die.

Abstract: Disclosed herein are microelectronics packages that include thermal pillars for at least localized extraction of generated heat and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies stacked on the substrate with at least one of the plurality of dies connected to the substrate. A heat spreader may be located proximate at least a portion of the plurality of dies. Respective thermal pillars from a plurality of thermal pillars may extend from at least one of the plurality dies to the heat spreader. Each of the plurality of thermal pillars may define a respective pathway from at least one of the plurality of dies to the heat spreader.

Abstract: Various embodiments disclosed relate to a semiconductor assembly having a ceramic or glass interposer for connecting dies within a semiconductor package. The present disclosure includes a ceramic or glass interposer having a carrier layer of substantially glass or ceramic material and a connecting layer having at least one dielectric layer and electrical routing therein.

Abstract: An electronic device comprises a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material; a stiffening layer including one of a ceramic or glass, the stiffening layer including a first surface contacting a first surface of the first RDL and including a through layer via (TLV); and multiple integrated circuit (ICs) arranged on a second surface of the first RDL and including bonding pads, wherein the conductive traces of the first RDL provide electrical continuity between at least one bonding pad of the ICs and at least one TLV of the stiffening layer.

Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate, including a core and a stiffener in the core, wherein the stiffener is along a perimeter of the core; and a die electrically coupled to the substrate.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; and a microelectronic subassembly electrically coupled to the substrate by interconnects, the microelectronic subassembly including an interposer having a surface; a first die electrically coupled to the surface of the interposer; a second die electrically coupled to the surface of the interposer; and a stiffener ring coupled to the surface of the interposer along the perimeter of the interposer.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate having a first surface and an opposing second surface; a die electrically coupled to the second surface of the substrate; and a stiffener attached to the first surface of the substrate configured to mitigate warpage of the die.

Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.

Abstract: A semiconductor memory arrangement includes a circuit board having at least a first layer and a second layer, a plurality of memory units, and a first control device and a second control device adapted to receive command and address signals. A first bus system is disposed in the first layer of the circuit board and coupled to the first control device and to a first group of memory units of the plurality of memory units to transmit the command and address signals to the first group of memory units. A second bus system is disposed in the second layer of the circuit board and coupled to the second control device and to a second group of memory units of the plurality of memory units to transmit the command and address signals to the second group of memory units.

Abstract: A memory module with a module board is disclosed, on the front side of which a plurality of first memory devices are arranged in rows. A plurality of second memory devices are arranged in rows on the back side. The first and second memory devices have a single chip each. Further, a first register device for providing first control signals to first rows of first memory devices and to first rows of second memory devices is provided. A second register device serves to provide first control signals to second rows of first memory devices and to second rows of second memory devices.

Abstract: A memory module with a module board is disclosed, on the front side of which a plurality of first memory devices are arranged in rows. A plurality of second memory devices are arranged in rows on the back side. The first and second memory devices have a single chip each. Further, a first register device for providing first control signals to first rows of first memory devices and to first rows of second memory devices is provided. A second register device serves to provide first control signals to second rows of first memory devices and to second rows of second memory devices.

Abstract: A semiconductor memory arrangement includes a circuit board having at least a first layer and a second layer, a plurality of memory units, and a first control device and a second control device adapted to receive command and address signals. A first bus system is disposed in the first layer of the circuit board and coupled to the first control device and to a first group of memory units of the plurality of memory units to transmit the command and address signals to the first group of memory units. A second bus system is disposed in the second layer of the circuit board and coupled to the second control device and to a second group of memory units of the plurality of memory units to transmit the command and address signals to the second group of memory units.