Abstract: A processing system includes a processor, a memory controller, and a memory subsystem. The memory controller includes a processor interface, a memory data interface, sequential transfer circuitry, and transaction processing logic. Randomly accessed data units of a first size are synchronously exchanged between the memory data interface of the memory controller and the memory subsystem via a transfer sequence comprising a predetermined plurality of sequential transfers of data units of a size smaller than the first size.

Abstract: A memory component, on a single integrated circuit, operated as a slave to an external master, includes a RAM, one or more configuration registers, data formatting logic, and associated control logic. The behavior of the memory component, and in particular the selection of a burst transfer format, is controllable via configuration register bits in the one or more configuration registers. Specifically, based on a format selection specified by the configuration bits, the control logic determines the sequence-length of the data transfers between the RAM and the external master. Other than the sequence-length, the data is not otherwise altered during the data transfers.

Abstract: A memory component, on a single integrated circuit, operated as a slave to an external master, includes a RAM, one or more configuration registers, data formatting logic, and associated control logic. The behavior of the memory component, and in particular the selection of a burst transfer format, is controllable via configuration register bits in the one or more configuration registers. Specifically, based on a format selection specified by the configuration bits, the control logic determines the sequence-length of the data transfers between the RAM and the external master. Other than the sequence-length, the data is not otherwise altered during the data transfers.

Abstract: A memory component, on a single integrated circuit, operated as a slave to an external master, includes a RAM, one or more configuration registers, data formatting logic, and associated control logic. The behavior of the memory component, and in particular the selection of a burst transfer format, is controllable via configuration register bits in the one or more configuration registers. Specifically, based on a format selection specified by the configuration bits, the control logic determines the sequence-length of the data transfers between the RAM and the external master. Other than the sequence-length, the data is not otherwise altered during the data transfers.

Abstract: A memory component, on a single integrated circuit, operated as a slave to an external master, includes a RAM, one or more configuration registers, data formatting logic, and associated control logic. The behavior of the memory component, and in particular the selection of a burst transfer format, is controllable via configuration register bits in the one or more configuration registers. Specifically, based on a format selection specified by the configuration bits, the control logic determines the sequence-length of the data transfers between the RAM and the external master. Other than the sequence-length, the data is not otherwise altered during the data transfers.

Abstract: A processing system includes a processor, a memory controller, and a memory subsystem. The memory controller includes a processor interface, a memory data interface, sequential transfer circuitry, and transaction processing logic. Randomly accessed data units of a first size are synchronously exchanged between the memory data interface of the memory controller and the memory subsystem via a transfer sequence comprising a predetermined plurality of sequential transfers of data units of a size smaller than the first size.

Abstract: A system includes a first and second integrated circuit and associated interconnect. The first integrated circuit is a memory component and includes a RAM, one or more configuration registers, and associated control logic. The second integrated circuit is a memory controller that is a master to the memory component. The behavior of the memory component, including selection from a number of different operating modes, is controllable via configuration register mode bits. The various modes include several transfer-length modes, where each mode corresponds to data transfers of a predetermined length. Based on the mode selection specified by the mode bits, the controller determines the length of the data transfers.

Abstract: A memory component, on a single integrated circuit, operated as a slave to an external master, includes a RAM, one or more configuration registers, data formatting logic, and associated control logic. The behavior of the memory component, and in particular the selection of a burst transfer format, is controllable via configuration register bits in the one or more configuration registers. Specifically, based on a format selection specified by the configuration bits, the control logic determines the sequence-length of the data transfers between the RAM and the external master. Other than the sequence-length, the data is not otherwise altered during the data transfers.

Abstract: A memory component on a single integrated circuit includes a RAM, one or more configuration registers, and an associated controller. The behavior of the memory component, including selection from a number of different operating modes, is controllable via configuration register mode bits. The various modes include several transfer-length modes, where each mode corresponds to data transfers of a predetermined length. Based on the mode selection specified by the mode bits, the controller determines the length of the data transfers.

Abstract: A multiprocessor system comprising a core memory (RAM), processing units (CPU.sub.1 -CPU.sub.j), each being provided with a cache memory (MCj), a directory (RG.sub.j) and a management processor (PG.sub.j); the core memory (RAM) is connected to an assembly of shift registers (RDM.sub.1 -RDM.sub.j) in such a way as to permit, in one cycle of the memory, a parallel transfer by reading or writing of data blocks; each cache memory (MC.sub.j) is connected to a shift register (RDP.sub.j)in such a way as to permit a parallel transfer by reading or writing of data blocks. An assembly of series connections, (LS.sub.1 -LS.sub.n) is provided between the assembly of memory shift registers and the assembly of processor shift registers to permit the transfer of data blocks between each pair of associated registers (RDM.sub.j -RDP.sub.j); the addresses of the data blocks can be transmitted between processor (CPU.sub.j) and the core memory (RAM) either by the series connections or by a common address bus (BUS A).

Abstract: A multiport series memory component for a multiprocessor system comprising an integrated circuit having a random access memory of a predetermined width corresponding to a block of information, an assembly of shift registers each of which has a size corresponding to the width of the memory unit, an internal parallel bus connecting the access of the memory unit to the shift registers, a shift register slection logic for validating the link on the internal bus between the memory unit and a predetermined shift register, and an assembly of extrnal input/output pins for the input of addresses to the memory unit for the input and validation of transfer commands in reading and writing of a block of information between the memory unit and the shift registers, for the input of a clock signal to each shift register, for bit-by-bit input of a block of information to each shift register and for the bit by bit output of a block of information from each shift register.