Abstract: A memory device to determine a voltage optimized to read a group of memory cells by reading the group of memory cells at a plurality of test voltages, computing bit counts at the test voltages respectively, and computing count differences in the bit counts for pairs of adjacent voltages in the test voltages. When a smallest one in the count differences is found at a side of a distribution of the count differences according to voltage, the memory device is configured to determine a location of an optimized read voltage, based on a ratio between a first count difference and a second count difference, where the first count difference is the smallest in the count differences, and the second count difference is closest in voltage to the first count difference.

Abstract: Methods, systems, and machine-readable storage medium for multi- tier data recovery utilizing a series of progressively more complex detection and decoding modes based on data from additional pages or wordlines. In one aspect, read data is obtained from at least one cell comprising a given page of a flash memory, and reliability values are generated for the cell from the read data. The reliability values are utilized to decode the read data for the given page. If the decoding of the read data fails, a series of successive decoding steps is performed, with each successive decoding step utilizing additional read data to generate reliability values for the decoding. In one example, reads of one or more additional pages in the same wordline are performed. In a second example, several read retries (soft reads) of the same wordline are performed. In a third example, one or more additional neighboring wordlines are read.

Abstract: A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.

Abstract: Data compression techniques are provided that remove redundancy across the boundary of compression search engines. An illustrative method comprises splitting the data frame into a plurality of sub-chunks; comparing at least two of the plurality of sub-chunks to one another to remove at least one sub-chunk from the plurality of sub-chunks that substantially matches at least one other sub-chunk to generate a remaining plurality of sub-chunks; generating matching sub-chunk information for data reconstruction identifying the at least one removed sub-chunk and the corresponding substantially matched at least one other sub-chunk; grouping the remaining plurality of sub-chunks into sub-units; removing substantially repeated patterns within the sub-units to generate corresponding compressed sub-units; and combining the compressed sub-units with the matching sub-chunk information to generate a compressed data frame.

Abstract: A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.

Abstract: A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.

Abstract: Read threshold voltage tracking techniques are provided for multiple dependent read threshold voltages using syndrome weights.

Abstract: Methods and apparatus are provided for read retry operations that estimate written data based on syndrome weights. One method comprises reading a codeword from a memory multiple times using multiple read reference voltages; obtaining a syndrome weight for each of the readings of the codeword; identifying a given reading of the codeword having a substantially minimum syndrome weight; and estimating a written value of the codeword based on the given reading. Two cell voltage probability distributions of cell voltages are optionally calculated for each possible cell state of the memory, based on the estimated written value and plurality of readings of the codeword. The cell voltage probability distributions are used to (i) dynamically select log likelihood ratio values for a failing page, (ii) determine a read reference voltage that gives a desired log likelihood ratio value, or (iii) dynamically select log likelihood ratio values for the page populations associated with the distributions.

Abstract: Adaptive read threshold voltage tracking techniques are provided that employ bit error rate estimation based on a non-linear syndrome weight mapping. An exemplary device comprises a controller configured to determine a bit error rate for at least one of a plurality of read threshold voltages in a memory using a non-linear mapping of a syndrome weight to the bit error rate for the at least one of the plurality of read threshold voltages.

Abstract: Data compression techniques are provided that remove redundancy across the boundary of compression search engines. An illustrative method comprises splitting the data frame into a plurality of sub-chunks; comparing at least two of the plurality of sub-chunks to one another to remove at least one sub-chunk from the plurality of sub-chunks that substantially matches at least one other sub-chunk to generate a remaining plurality of sub-chunks; generating matching sub-chunk information for data reconstruction identifying the at least one removed sub-chunk and the corresponding substantially matched at least one other sub-chunk; grouping the remaining plurality of sub-chunks into sub-units; removing substantially repeated patterns within the sub-units to generate corresponding compressed sub-units; and combining the compressed sub-units with the matching sub-chunk information to generate a compressed data frame.

Abstract: A syndrome weight of failed decoding attempts is used to select parameters for future read retry operations. The following exemplary steps are performed until a decoding success or a predefined limited number of readings is reached: (i) reading a codeword using different read threshold voltages; (ii) mapping the readings to a corresponding likelihood value using a likelihood value assignment; and (iii) recording a syndrome weight for failed decoding attempts of the readings using the different read threshold voltages.

Abstract: An apparatus for reading a flash memory includes a read controller operable to read the flash memory to yield read patterns, a likelihood generator operable to map the read patterns to likelihood values, a decoder operable to decode the likelihood values, a data state storage operable to retrieve the likelihood values for which decoding failed, and a selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding.

Abstract: Methods and apparatus are provided for multi-tier detection and decoding in flash memory devices. Data from a flash memory device is processed by obtaining one or more quantized estimates of a voltage stored on at least one bit of a cell of the flash memory device from the flash memory device; converting the one or more quantized estimates for the at least one bit to a reliability value; and decoding the at least one bit using the reliability value to obtain a value written for the at least one bit.

Abstract: An apparatus includes an interface and a control circuit. The interface may be configured to process read/write operations to/from a memory. The control circuit may be configured to create dependencies between a current bit in a sequence of data bits and neighboring bits in the sequence of data bits to generate mapped bits in response to a condition in a region of the memory being true, write the mapped bits among at least two memory cells in the region of the memory with at least two of the mapped bits stored in each of the memory cells, where the dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state, and write the sequence of data bits in the region of the memory in response to the condition in the region of the memory being false.

Abstract: Independent read threshold voltage tracking techniques are provided for multiple dependent read threshold voltages using syndrome weights.

Abstract: Adaptive read threshold voltage tracking techniques are provided that employ bit error rate estimation based on a non-linear syndrome weight mapping. An exemplary device comprises a controller configured to determine a bit error rate for at least one of a plurality of read threshold voltages in a memory using a non-linear mapping of a syndrome weight to the bit error rate for the at least one of the plurality of read threshold voltages.

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of read/write operations to/from the memory, receive a codeword from the memory, generate a plurality of syndromes of the codeword at a plurality of possible code rates, generate a plurality of count values by counting a number of unsatisfied parity checks in each of the plurality of syndromes, generate a plurality of normalized values by dividing the plurality of count values by a plurality of lengths of the plurality of possible code rates respectively, and determine a bit error rate value of the memory based on a lowest value among the plurality of normalized values.

Abstract: A syndrome weight of failed decoding attempts is used to select parameters for future read retry operations. The following exemplary steps are performed until a decoding success or a predefined limited number of readings is reached: (i) reading a codeword using different read threshold voltages; (ii) mapping the readings to a corresponding likelihood value using a likelihood value assignment; and (iii) recording a syndrome weight for failed decoding attempts of the readings using the different read threshold voltages.

Abstract: Methods and apparatus are provided for read retry operations that estimate written data based on syndrome weights. One method comprises reading a codeword from a memory multiple times using multiple read reference voltages; obtaining a syndrome weight for each of the readings of the codeword; identifying a given reading of the codeword having a substantially minimum syndrome weight; and estimating a written value of the codeword based on the given reading. Two cell voltage probability distributions of cell voltages are optionally calculated for each possible cell state of the memory, based on the estimated written value and plurality of readings of the codeword. The cell voltage probability distributions are used to (i) dynamically select log likelihood ratio values for a failing page. (ii) determine a read reference voltage that gives a desired log likelihood ratio value, or (iii) dynamically select log likelihood ratio values for the page populations associated with the distributions.

Abstract: An apparatus includes an interface and a control circuit. The interface may be configured to process read/write operations to/from a memory. The control circuit may be configured to create dependencies between a current bit in a sequence of data bits and neighboring bits in the sequence of data bits to generate mapped bits in response to a condition in a region of the memory being true, write the mapped bits among at least two memory cells in the region of the memory with at least two of the mapped bits stored in each of the memory cells, where the dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state, and write the sequence of data bits in the region of the memory in response to the condition in the region of the memory being false.