Patents by Inventor Abderrezak Marzaki

Abderrezak Marzaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10991710
    Abstract: A non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: April 27, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Quentin Hubert, Abderrezak Marzaki, Julien Delalleau
  • Publication number: 20210118725
    Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.
    Type: Application
    Filed: October 12, 2020
    Publication date: April 22, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Franck JULIEN, Abderrezak MARZAKI
  • Patent number: 10971578
    Abstract: The disclosure concerns a capacitive component including a trench and, vertically in line with the trench, first portions of a first silicon oxide layer and first portions of second and third conductive layers including polysilicon or amorphous silicon, the first portion of the first layer being between and in contact with the first portions of the second and third layers.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: April 6, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak Marzaki, Pascal Fornara
  • Patent number: 10943862
    Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: March 9, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Abderrezak Marzaki, Arnaud Regnier, Stephan Niel
  • Patent number: 10943973
    Abstract: A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: March 9, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Patent number: 10937746
    Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunneling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: March 2, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak Marzaki, Pascal Fornara
  • Publication number: 20210057329
    Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.
    Type: Application
    Filed: August 21, 2019
    Publication date: February 25, 2021
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Abderrezak MARZAKI, Arnaud REGNIER, Stephan NIEL
  • Publication number: 20210057358
    Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed to detect a DFA attack by fault injection into the integrated circuit.
    Type: Application
    Filed: November 6, 2020
    Publication date: February 25, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Abderrezak MARZAKI
  • Publication number: 20210035996
    Abstract: A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.
    Type: Application
    Filed: July 27, 2020
    Publication date: February 4, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Franck JULIEN, Abderrezak MARZAKI
  • Patent number: 10892234
    Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed, in a first configuration, to detect a thinning of the substrate via its rear face, and in a second configuration, to detect a DFA attack by fault injection into the integrated circuit.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Abderrezak Marzaki
  • Publication number: 20210005612
    Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Abderrezak MARZAKI, Arnaud REGNIER, Stephan NIEL, Quentin HUBERT, Thomas CABOUT
  • Publication number: 20210005613
    Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Abderrezak MARZAKI, Arnaud REGNIER, Stephan NIEL, Quentin HUBERT, Thomas CABOUT
  • Patent number: 10886283
    Abstract: An integrated circuit includes at least one antifuse element. The antifuse element is formed from a semiconductor substrate, a trench extending down from a first face of the semiconductor substrate into the semiconductor substrate, a first conductive layer housed in the trench and extending down from the first face of the semiconductor substrate into the semiconductor substrate, a dielectric layer on the first face of the semiconductor substrate, and a second conductive layer on the dielectric layer. A program transistor selectively electrically couples the second conductive layer to a program voltage in response to a program signal. A program/read transistor selectively electrically couples the first conductive layer to a ground voltage in response to the program signal and in response to a read signal. A read transistor selectively electrically couples the second conductive layer to a read amplifier in response to the read signal.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: January 5, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak Marzaki, Pascal Fornara
  • Publication number: 20200411454
    Abstract: A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A device is configured to detect a thinning of the semiconductor substrate from the back face. The device includes at least one trench that extends within the semiconductor well between two peripheral locations from the front face down to a location situated at a distance from a bottom of the semiconductor well. The trench is electrically isolated from the semiconductor well. A detection circuit is configured to measure a physical quantity representative of well electrical resistance between two contact areas respectively situated on either side of the at least one first trench.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak MARZAKI
  • Patent number: 10879233
    Abstract: A capacitive element is fabricated by forming a sacrificial trench isolation and directionally etching through the sacrificial trench isolation and into an underlying semiconductor substrate to form an electrode trench. The electrode trench is then clad with an insulating material and filled with a conductive material. The conductive fill provided one capacitor electrode and the semiconductor substrate forms another capacitor electrode, with the insulating material cladding forming the capacitor dielectric layer.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 29, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Patent number: 10868199
    Abstract: A standard integrated cell includes a semiconductor region with a functional domain for logic circuits including a transistor and an adjacent continuity domain that extends out to an edge of the standard integrated cell. The edge is configured to be adjacent to another continuity domain of another standard integrated cell. The standard integrated cell further includes a capacitive element. This capacitive element may be housed in the continuity domain, for example at or near the edge. Alternatively, the capacitive element may be housed at a location which extends around a substrate region of the transistor.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: December 15, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Patent number: 10818669
    Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 27, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Abderrezak Marzaki, Arnaud Regnier, Stephan Niel, Quentin Hubert, Thomas Cabout
  • Patent number: 10804223
    Abstract: A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A device is configured to detect a thinning of the semiconductor substrate from the back face. The device includes at least one trench that extends within the semiconductor well between two peripheral locations from the front face down to a location situated at a distance from a bottom of the semiconductor well. The trench is electrically isolated from the semiconductor well. A detection circuit is configured to measure a physical quantity representative of well electrical resistance between two contact areas respectively situated on either side of the at least one first trench.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: October 13, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Publication number: 20200286896
    Abstract: A capacitive element is located in an active region of the substrate and on a front face of the substrate. The capacitive element includes a first electrode and a second electrode. The first electrode is formed by a first conductive region and the active region. The second electrode is formed by a second conductive region and a monolithic conductive region having one part covering a surface of said front face and at least one part extending into the active region perpendicularly to said front face. The first conductive region is located between and is insulated from the monolithic conductive region and a second conductive region.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 10, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak MARZAKI
  • Publication number: 20200286986
    Abstract: A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 10, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak MARZAKI