Abstract: An integrated circuit includes lateral isolation regions delimiting active regions in a semiconductor substrate. A trench is etched extending vertically in depth into the semiconductor substrate and intended to pass through the lateral isolation regions and the active regions. The formation of the lateral isolation regions includes forming sacrificial lateral isolation regions positioned at a location of the etching of the trench which passes through the active regions.

Abstract: A method for detecting orientation of an integrated circuit is disclosed. The method includes moving, in response to a gravitational force, a mobile metallic piece in an evolution zone of a housing. The housing is formed in an interconnect region of the integrated circuit. The housing includes walls defining the evolution zone. The walls are formed within multiple metallization levels of the interconnect region. The walls include a floor wall and a ceiling wall. At least one of the floor wall and ceiling wall incorporate a pointed element directing its pointed region towards the mobile metallic piece. The pointed element delimits an open crater in a concave part of a projection. The method further includes creating an electrical signal by movement of the mobile metallic piece at a plurality of electrically conducting elements positioned at boundary points of the evolution zone and detecting the electrical signal by a detector.

Abstract: The integrated circuit includes a logic part including standard cells arranged in parallel rows along a first direction and in an alternation of complementary semiconductor wells. Among the standard cells, at least one capacitive filling structure belongs to two adjacent rows and includes a capacitive interface between a conductive armature and the first well, the extent of the second well in the first direction being interrupted over the length of the capacitive filling structure so that the first well occupies in the second direction the width of the two adjacent rows of the capacitive filling structure. A conductive structure electrically connects the second well on either side of the capacitive filling structure.

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

Abstract: A bipolar transistor includes a common collector region comprising a buried semiconductor layer and an annular well. A well region is surrounded by the annular well and delimited by the buried semiconductor layer. A first base region and a second base region are formed by the well region and separated from each other by a vertical gate structure. A first emitter region is implanted in the first base region, and a second emitter region is implanted in the second base region. A conductor track electrically couples the first emitter region and the second base region to configure the bipolar transistor as a Darlington-type device. Structures of the bipolar transistor may be fabricated in a co-integration with a non-volatile memory cell.

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

Abstract: A triple-gate MOS transistor is manufactured in a semiconductor substrate including at least one active region laterally surrounded by electrically isolating regions. Trenches are etched on either side of an area of the active region configured to form a channel for the transistor. An electrically isolating layer is deposited on an internal surface of each of the trenches. Each of the trenches is then filled with a semiconductive or electrically conductive material up to an upper surface of the active region so as to form respective vertical gates on opposite sides of the channel. An electrically isolating layer is then deposited on the upper surface of the area of the active region at the channel of the transistor. At least one semiconductive or electrically conductive material then deposited on the electrically isolating layer formed at the upper surface of the active region to form a horizontal gate of the transistor.

Abstract: An integrated circuit includes a substrate having a front face. A capacitive element includes, over a surface at the front face, a stack made of: a first conductive armature, a dielectric interface region over the first conductive armature, and a second conductive armature over the dielectric interface region. The first conductive armature includes a gate metal layer located over a layer of a material with a high dielectric constant.

Abstract: A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor substrate via the rear face thereof is formed on and in the semiconductor wells. The device is a non-inverting buffer including an input terminal and an output terminal, the device being powered between a supply terminal and a reference terminal where the buried semiconductor layer provides the supply terminal. A control circuit delivers an input signal in a first state to the input terminal and outputs a control signal indicating a detection of a thinning of the substrate if a signal generated at the output terminal in response to the input signal is in a second state different from the first state.

Abstract: A triple-gate MOS transistor is manufactured in a semiconductor substrate including at least one active region laterally surrounded by electrically isolating regions. Trenches are etched on either side of an area of the active region configured to form a channel for the transistor. An electrically isolating layer is deposited on an internal surface of each of the trenches. Each of the trenches is then filled with a semiconductive or electrically conductive material up to an upper surface of the active region so as to form respective vertical gates on opposite sides of the channel. An electrically isolating layer is then deposited on the upper surface of the area of the active region at the channel of the transistor. At least one semiconductive or electrically conductive material then deposited on the electrically isolating layer formed at the upper surface of the active region to form a horizontal gate of the transistor.

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type embedded in a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type embedded in a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth doped wells, the first wall including a conductive or semiconductor core and an insulating liner, the insulating liner extending between the conductive or semiconductor core and the second and fourth doped wells, and a stack of layers comprising a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer, the first insulating layer being in contact with the second and fourth doped wells.

Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type in contact with a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type in contact with a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth wells, the first wall including a conductive or semiconductor core and an insulating sheath, a stack of layers including a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer at least partially covering the second and fourth wells and a third semiconductor layer located below the second and fourth wells and the first wall.

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed to detect a DFA attack by fault injection into the integrated circuit.

Abstract: In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

Abstract: An integrated circuit includes transistor. That transistor is manufactured using a process including the following steps: forming a first gate region; depositing dielectric layers accumulating on sides of the first gate region to form regions of spacers having a width; etching to remove a part of the deposited dielectric layers accumulated on the sides of the first gate region to reduce the width of the regions of spacers; performing a first implantation of dopants aligned on the regions of spacers to form first lightly doped conduction regions of the transistor; and performing a second implanting of dopants to form first more strongly doped conduction regions of the transistor.

Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.