Abstract: An apparatus and method of operating the apparatus are disclosed, where the apparatus has translation circuitry to perform translations of input data to generate a translation response comprising translated data. The translation is performed in dependence on translation configuration data stored in data storage. A processing element determines an associated error detection code in dependence on the input data and on the translated data, and causes the translation configuration data and the associated error detection code to be stored in the data storage. When translation of the input data is performed by the translation circuitry the translation configuration data and its associated error detection code are retrieved from the data storage and the input data is translated into the translated data in dependence on the translation configuration data. A verification error detection code is calculated in dependence on the input data and on the translated data.

Abstract: An apparatus and method of operating the apparatus are disclosed, where the apparatus has translation circuitry to perform translations of input data to generate a translation response comprising translated data. The translation is performed in dependence on translation configuration data stored in data storage. A processing element determines an associated error detection code in dependence on the input data and on the translated data, and causes the translation configuration data and the associated error detection code to be stored in the data storage. When translation of the input data is performed by the translation circuitry the translation configuration data and its associated error detection code are retrieved from the data storage and the input data is translated into the translated data in dependence on the translation configuration data. A verification error detection code is calculated in dependence on the input data and on the translated data.

Abstract: An interrupt controller, and method of operation of such an interrupt controller, are provided. The interrupt controller has an interrupt source interface for receiving interrupts from one or more interrupt sources, and a plurality of output interfaces, where each output interface is associated with a processing device that can execute an interrupt service routine to process an interrupt request issued to that processing device. The interrupt source interface has transaction generation circuitry to generate, for each received interrupt, an original transaction to represent the interrupt and a duplicate transaction to represent the interrupt. Buffer circuitry then buffers the original transaction and the duplicate transaction for each received interrupt, and selection circuitry is provided for selecting transactions from the buffer circuitry, and for routing each selected transaction for receipt by the output interface identified by an address portion of the selected transaction.