Abstract: A tracking circuit in a memory unit which generates sense enable signals at optimal time instances. The tracking circuit includes a scalable driver block containing a number of dummy cells, each having a drive strength identical to the drive strength of a cell in a memory array. The dummy cells are turned on and drive a column as would the memory cells in the memory array. As a result, the scalable driver block approximates the delay caused by (a number of rows in) a column at least when the number of rows is large. An inverse control logic emulates the delay in case of a smaller number of rows, and one of the inverse control logic and the scalable driver blocks provides a pulse, which is used to trigger a sense operation.