Abstract: An energy-efficient capacitance-to-digital converter (CDC) is provided that utilizes a capacitance-domain successive approximation (SAR) technique. Unlike SAR analog-to-digital converters (ADCs), analysis shows that for SAR CDCs, the comparator offset voltage will result in signal-dependent and parasitic-dependent conversion errors, which necessitates an op-amp-based implementation. The inverter-based SAR CDC contemplated herein provides robust, energy-efficient, and fast operation. The inverter-based SAR CDC may include a hybrid coarse-fine programmable capacitor array. The design of example embodiments is insensitive to analog references, and thus achieves very low temperature sensitivity without the need for calibration. Moreover, this design achieves improved energy efficiency.

Abstract: Circuitry and techniques are described herein for performing accurate and low power conversion of an analog value into a digital value. According to some aspects, this disclosure describes a successive approximation register (SAR) analog to digital converter (ADC). According to some aspects the SAR ADC comprises an active integrator between a sample and hold stage and a comparator stage. The active integrator operates differently dependent on whether the SAR ADC is operated in a sample phase or a conversion phase. According to other aspects, the SAR ADC utilizes a ring oscillator-based comparator to compare a sampled analog input value to a plurality of reference values to determine a digital value representing the analog value.

Abstract: Circuitry and techniques are described herein for performing accurate and low power conversion of an analog value into a digital value. According to some aspects, this disclosure describes a successive approximation register (SAR) analog to digital converter (ADC). According to some aspects the SAR ADC comprises an active integrator between a sample and hold stage and a comparator stage. The active integrator operates differently dependent on whether the SAR ADC is operated in a sample phase or a conversion phase. According to other aspects, the SAR ADC utilizes a ring oscillator-based comparator to compare a sampled analog input value to a plurality of reference values to determine a digital value representing the analog value.

Abstract: An energy-efficient capacitance-to-digital converter (CDC) is provided that utilizes a capacitance-domain successive approximation (SAR) technique. Unlike SAR analog-to-digital converters (ADCs), analysis shows that for SAR CDCs, the comparator offset voltage will result in signal-dependent and parasitic-dependent conversion errors, which necessitates an op-amp-based implementation. The inverter-based SAR CDC contemplated herein provides robust, energy-efficient, and fast operation. The inverter-based SAR CDC may include a hybrid coarse-fine programmable capacitor array. The design of example embodiments is insensitive to analog references, and thus achieves very low temperature sensitivity without the need for calibration. Moreover, this design achieves improved energy efficiency.

Abstract: An energy-efficient capacitance-to-digital converter (CDC) is provided that utilizes a capacitance-domain successive approximation (SAR) technique. Unlike SAR analog-to-digital converters (ADCs), analysis shows that for SAR CDCs, the comparator offset voltage will result in signal-dependent and parasitic-dependent conversion errors, which necessitates an op-amp-based implementation. The inverter-based SAR CDC contemplated herein provides robust, energy-efficient, and fast operation. The inverter-based SAR CDC may include a hybrid coarse-fine programmable capacitor array. The design of example embodiments is insensitive to analog references, and thus achieves very low temperature sensitivity without the need for calibration. Moreover, this design achieves improved energy efficiency.

Abstract: An energy-efficient capacitance-to-digital converter (CDC) is provided that utilizes a capacitance-domain successive approximation (SAR) technique. Unlike SAR analog-to-digital converters (ADCs), analysis shows that for SAR CDCs, the comparator offset voltage will result in signal-dependent and parasitic-dependent conversion errors, which necessitates an op-amp-based implementation. The inverter-based SAR CDC contemplated herein provides robust, energy-efficient, and fast operation. The inverter-based SAR CDC may include a hybrid coarse-fine programmable capacitor array. The design of example embodiments is insensitive to analog references, and thus achieves very low temperature sensitivity without the need for calibration. Moreover, this design achieves improved energy efficiency.