Patents by Inventor Abdullah Ahmed
Abdullah Ahmed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7382638Abstract: A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.Type: GrantFiled: July 9, 2007Date of Patent: June 3, 2008Assignee: MOSAID Technologies IncorporatedInventors: Stanley Jeh-Chun Ma, Peter P. Ma, Valerie Lines, Peter Gillingham, Robert McKenzie, Abdullah Ahmed
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Publication number: 20070258277Abstract: A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.Type: ApplicationFiled: July 9, 2007Publication date: November 8, 2007Inventors: Stanley Ma, Peter Ma, Valerie Lines, Peter Gillingham, Robert McKenzie, Abdullah Ahmed
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Patent number: 7251148Abstract: A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.Type: GrantFiled: November 9, 2005Date of Patent: July 31, 2007Assignee: Mosaid Technologies IncorporatedInventors: Stanley Jeh-Chun Ma, Peter P. Ma, Valerie Lines, Peter Gillingham, Robert McKenzie, Abdullah Ahmed
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Publication number: 20060083041Abstract: A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.Type: ApplicationFiled: November 9, 2005Publication date: April 20, 2006Inventors: Stanley Ma, Peter Ma, Valerie Lines, Peter Gillingham, Robert McKenzie, Abdullah Ahmed
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Patent number: 6987682Abstract: A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. the circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.Type: GrantFiled: May 1, 2001Date of Patent: January 17, 2006Assignee: MOSAID Technologies IncorporatedInventors: Stanley Jeh-Chun Ma, Peter P. Ma, Valerie Lines, Peter Gillingham, Robert McKenzie, Abdullah Ahmed
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Patent number: 6873531Abstract: A differential sensing amplifier for content addressable memory is disclosed. In the differential sensing amplifier there is a detection circuit for detecting at an input node a change in an input signal comprising, a differential amplifier having a sense node and a reference node, a means for alternating the differential amplifier between a precharge phase and a sense phase, a precharge means for providing an input signal precharge voltage to the input signal via an input device, said input device selectively coupling the sense node to the input signal upon a change in the input signal, and a reference means for providing the reference node with a reference signal that continuously tracks the input precharge voltage during the precharge phase and actively maintains the input signal precharge voltage during the sense phase.Type: GrantFiled: May 31, 2002Date of Patent: March 29, 2005Assignee: MOSAID Technologies IncorporatedInventors: Abdullah Ahmed, Jin Ki Kim
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Patent number: 6744688Abstract: A system and method for reduction of power consumed by a searchline buffer and control circuit during a CAM search-and-compare operation. The data buffer circuit samples one bit of a search word and a mask bit for driving a pair of complementary searchlines with the appropriate logic levels. The complementary searchlines are precharged to a mid-point voltage level between the high logic level voltage and the low logic level voltage during a precharge phase. The mid-point voltage level is applied on each searchline by sharing charge from the searchline at the high logic level voltage with the searchline at the low logic level voltage. Additional control logic compares the searchline data of the current search-and-compare operation with the next search-and-compare operation, to inhibit searchline precharging when both searchline data are at the same logic level.Type: GrantFiled: February 4, 2003Date of Patent: June 1, 2004Assignee: MOSAID Technologies IncorporatedInventors: Peter B. Gillingham, Abdullah Ahmed
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Patent number: 6667924Abstract: A signal detection circuit that provides multilevel sense detection that is both fast and has low power consumption. The signal detection circuit has amplifying means for providing at least one output corresponding to the difference in voltage levels between a sense node and a reference node. Input means apply a voltage level onto the sense node, and reference means apply a reference voltage onto the reference node. The input and reference means have substantially similar electrical characteristics, however, the reference means includes a reference device that is physically larger than a corresponding device of the input means.Type: GrantFiled: December 10, 2002Date of Patent: December 23, 2003Assignee: Mosaid Technologies IncorporatedInventors: Abdullah Ahmed, Valerie L. Lines
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Publication number: 20030161194Abstract: A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. the circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.Type: ApplicationFiled: March 10, 2003Publication date: August 28, 2003Inventors: Stanley Jeh-Chun Ma, Peter P Ma, Valerie Lines, Peter Gillingham, Robert McKenzie, Abdullah Ahmed
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Publication number: 20030161209Abstract: A system and method for reduction of power consumed by a searchline buffer and control circuit during a CAM search-and-compare operation. The data buffer circuit samples one bit of a search word and a mask bit for driving a pair of complementary searchlines with the appropriate logic levels. The complementary searchlines are precharged to a mid-point voltage level between the high logic level voltage and the low logic level voltage during a precharge phase. The mid-point voltage level is applied on each searchline by sharing charge from the searchline at the high logic level voltage with the searchline at the low logic level voltage. Additional control logic compares the searchline data of the current search-and-compare operation with the next search-and-compare operation, to inhibit searchline precharging when both searchline data are at the same logic level.Type: ApplicationFiled: February 4, 2003Publication date: August 28, 2003Inventors: Peter B. Gillingham, Abdullah Ahmed
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Patent number: 6608788Abstract: An architecture and method for fast precharge of bitlines in a densely packed, dynamic content addressable memory is disclosed. The dynamic content addressable memory cells are arranged according to an open bitline architecture to obtain high packing density. The bitlines are precharged through equalization between every two adjacent open bitline pairs. More specifically, a bitline and its adjacent neighboring bitline on the same side of the bitline sense amplifiers are equalized at several locations along the bitlines such that they are equalized at high speed, which is typically not available in open bitline architectures. Hence the adjacent bitlines are precharged in a manner similar to a folded bitline architecture. Additional equalization circuits are connected between the complementary bitlines of each open bitline pair, therefore during the precharge phase, all four bitlines of the two open bitline pairs are equalized with each other.Type: GrantFiled: November 8, 2002Date of Patent: August 19, 2003Assignee: Mosaid Technologies IncorporatedInventors: Peter P Ma, Abdullah Ahmed, Valerie L Lines
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Publication number: 20030081474Abstract: A signal detection circuit that provides multilevel sense detection that is both fast and has low power consumption. The signal detection circuit has amplifying means for providing at least one output corresponding to the difference in voltage levels between a sense node and a reference node. Input means apply a voltage level onto the sense node, and reference means apply a reference voltage onto the reference node. The input and reference means have substantially similar electrical characteristics, however, the reference means includes a reference device that is physically larger than a corresponding device of the input means.Type: ApplicationFiled: December 10, 2002Publication date: May 1, 2003Inventors: Abdullah Ahmed, Valerie L. Lines
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Publication number: 20030072205Abstract: An architecture and method for fast precharge of bitlines in a densely packed, dynamic content addressable memory is disclosed. The dynamic content addressable memory cells are arranged according to an open bitline architecture to obtain high packing density. The bitlines are precharged through equalization between every two adjacent open bitline pairs. More specifically, a bitline and its adjacent neighbouring bitline on the same side of the bitline sense amplifiers are equalized at several locations along the bitlines such that they are equalized at high speed, which is typically not available in open bitline architectures. Hence the adjacent bitlines are precharged in a manner similar to a folded bitline architecture. Additional equalization circuits are connected between the complementary bitlines of each open bitline pair, therefore during the precharge phase, all four bitlines of the two open bitline pairs are equalized with each other.Type: ApplicationFiled: November 8, 2002Publication date: April 17, 2003Inventors: Peter P. Ma, Abdullah Ahmed, Valerie L. Lines
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Patent number: 6538947Abstract: A method for detecting n match conditions within a CAM array. The method consists of precharging a sense node and a reference node of a differential amplifier in an inactive state to a supply voltage level. The reference node voltage level is then changed to a reference voltage level between a voltage level corresponding to n match condition signals and n−1 match condition signals by turning on a reference device, The sense node voltage level is changed to a voltage level corresponding to a number of match condition signals by turning on a corresponding number of matchline devices, and the reference voltage level is compared to the voltage level corresponding to the number of match condition signals by switching the differential amplifier to an active state. An output signal corresponding to the result of the comparison is then provided from the differential amplifier. The method can further include a step of switching the differential amplifier to the inactive state when the output signal is provided.Type: GrantFiled: September 24, 2001Date of Patent: March 25, 2003Assignee: Mosaid Technologies IncorporatedInventors: Abdullah Ahmed, Valerie L. Lines
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Patent number: 6525586Abstract: A programmable delay element is provided for delaying a digital input signal. The programmable delay element comprises a discharge capacitor adapted to be precharged to a predetermined voltage in response to a first transition of the digital input signal. A transistor switch of a first type is provided for precharging the discharge capacitor to a predetermined voltage. A discharge current source is connected via a sense node to the discharge capacitor for discharging the capacitor in response to a subsequent opposite transition of the digital input signal. A transistor switch of a second type is provided for connecting the discharge capacitor to the discharge current source and thereby discharging the discharge capacitor. A reference voltage source is provided for applying a reference voltage to a reference node.Type: GrantFiled: November 9, 2001Date of Patent: February 25, 2003Assignee: Genesis Microchip, Inc.Inventors: Abdullah Ahmed, Sami Bizzan, Lawrence A. Prather
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Patent number: 6522596Abstract: A system and method for reduction of power consumed by a searchline buffer and control circuit during a CAM search-and-compare operation. The data buffer circuit samples one bit of a search word and a mask bit for driving a pair of complementary searchlines with the appropriate logic levels. The complementary searchlines are precharged to a mid-point voltage level between the high logic level voltage and the low logic level voltage during a precharge phase. The mid-point voltage level is applied on each searchline by sharing charge from the searchline at the high logic level voltage with the searchline at the low logic level voltage. Additional control logic compares the searchline data of the current search-and-compare operation with the next search-and-compare operation, to inhibit searchline precharging when both searchline data are at the same logic level.Type: GrantFiled: June 28, 2001Date of Patent: February 18, 2003Assignee: Mosaid Technologies IncorporatedInventors: Peter B. Gillingham, Abdullah Ahmed
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Publication number: 20030016580Abstract: An architecture and method for fast precharge of bitlines in a densely packed, dynamic content addressable memory is disclosed. The dynamic content addressable memory cells are arranged according to an open bitline architecture to obtain high packing density. The bitlines are precharged through equalization between every two adjacent open bitline pairs. More specifically, a bitline and its adjacent neighbouring bitline on the same side of the bitline sense amplifiers are equalized at several locations along the bitlines such that they are equalized at high speed, which is typically not available in open bitline architectures. Hence the adjacent bitlines are precharged in a manner similar to a folded bitline architecture. Additional equalization circuits are connected between the complementary bitlines of each open bitline pair, therefore during the precharge phase, all four bitlines of the two open bitline pairs are equalized with each other.Type: ApplicationFiled: September 21, 2001Publication date: January 23, 2003Inventors: Peter P. Ma, Abdullah Ahmed, Valerie L. Lines
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Patent number: 6504775Abstract: An architecture and method for fast precharge of bitlines in a densely packed, dynamic content addressable memory is disclosed. The dynamic content addressable memory cells are arranged according to an open bitline architecture to obtain high packing density. The bitlines are precharged through equalization between every two adjacent open bitline pairs. More specifically, a bitline and its adjacent neighbouring bitline on the same side of the bitline sense amplifiers are equalized at several locations along the bitlines such that they are equalized at high speed, which is typically not available in open bitlines architectures. Hence the adjacent bitlines are precharged in a manner similar to a folded bitline architecture. Additional equalization circuits are connected between the complementary bitlines of each open bitline pair, therefore during the precharge phase, all four bitlines of the two open bitline pairs are equalized with each other.Type: GrantFiled: September 21, 2001Date of Patent: January 7, 2003Assignee: Mosaid Technologies Incorporated KanataInventors: Peter P Ma, Abdullah Ahmed, Valerie L Lines
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Patent number: 6483733Abstract: A dynamic content addressable memory (CAM) is disclosed. The dynamic content addressable memory includes at least two pairs of bitlines coupled to opposite sides of at least two sense amplifiers in an open bitline configuration. Each bitline of each pair of bitlines is coupled to one of the at least two sense amplifiers, and a plurality of ternary dynamic content addressable memory cells are coupled to each of the at least pairs of bitlines. Each ternary dynamic content addressable memory cell is also coupled to a pair of search lines, a matchline, a word line and a discharge line, and further stores two bites of data in stacked capacitor storage cells. The bitlines on either side of the sense amlifiers are of equal length, and the pair of searchlines are arranged parallel to the bitlines.Type: GrantFiled: October 17, 2001Date of Patent: November 19, 2002Assignee: Mosaid Technologies IncorporatedInventors: Valerie Lines, Peter B. Gillingham, Abdullah Ahmed, Tomasz Wojcicki
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Publication number: 20020145452Abstract: A differential sensing amplifier for content addressable memory is disclosed. In the differential sensing amplifier there is a detection circuit for detecting at an input node a change in an input signal comprising, a differential amplifier having a sense node and a reference node, a means for alternating the differential amplifier between a precharge phase and a sense phase, a precharge means for providing an input signal precharge voltage to the input signal via an input device, said input device selectively coupling the sense node to the input signal upon a change in the input signal, and a reference means for providing the reference node with a reference signal that continuously tracks the input precharge voltage during the precharge phase and actively maintains the input signal precharge voltage during the sense phase.Type: ApplicationFiled: May 31, 2002Publication date: October 10, 2002Inventors: Abdullah Ahmed, Jin Ki Kim