Patents by Inventor Abdullah Cavus

Abdullah Cavus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090045437
    Abstract: The disclosure relates to a method for forming an intermediate lattice transition buffer layer. The method includes: (a) depositing a first graded InAlAs layer on a substrate at a first constant temperature, the first graded InAlAs layer having an In/AI composition ratio which increases across the buffer layer from a first level to a second level; (b) annealing at least the first graded InAlAs layer; (c) depositing the second graded InAlAs layer on the first graded InAlAs layer at the first constant temperature, the second graded InAlAs layer having an In/Al composition ratio which increases across the buffer layer from the second level to a third level; and (d) annealing at least the second graded InAlAs layer; the buffer layer being formed under Groups III/V overpressure.
    Type: Application
    Filed: August 15, 2007
    Publication date: February 19, 2009
    Applicant: Northrop Grumman Space & Mission Systems Corp.
    Inventors: Rajinder Sandhu, Abdullah Cavus, Cedric Monier, Augusto Gutierrez
  • Publication number: 20080230803
    Abstract: A semiconductor device that is fabricated by metamorphic epitaxial growth processes, and includes a combined graded base and active layer having a thickness less than 5000 ?. In one non-limiting embodiment, the semiconductor device is an HBT device that includes a combined doped graded buffer and sub-collector layer having a thickness less than 5000 ?, and a concentration of indium of about 86% at a top of the combined layer.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 25, 2008
    Applicant: Northrop Grumman Space & Mission Systems Corp.
    Inventors: Cedric Monier, Randy Sandhu, Abdullah Cavus, Augusto Gutierrez-Aitken
  • Patent number: 6365478
    Abstract: A solid state electronic device (40) comprising a substrate (30) and layers (32 and 34) is fabricated to control the formation of crystalline defects to control at least one characteristic of the device, such as current gain beta. The formation of crystalline defects preferably is controlled by controlling the temperature of the substrate, layers or both.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: April 2, 2002
    Assignee: TRW Inc.
    Inventors: Thomas R. Block, Michael Wojtowitz, Abdullah Cavus