Patents by Inventor Abdulrahman Alaql
Abdulrahman Alaql has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11797736Abstract: A method of obfuscating a circuit design includes, in part, receiving a netlist of the circuit design, splitting the circuit design into a multitude of partitions, transforming each partitions so as to obfuscate each partition, and stitching the multitude of transformed partitions to form the obfuscated circuit. The netlist may be a register transfer level netlist. The number and the size of partitions may vary. The partitions may be distributed throughout the entirety of the design. The method may further include generating a randomized circuit associated with at least a subset of the partitions, and merging each partition with the partition's associated randomized circuit. The method may further include quantifying the amount of transformation associated with each partition. The method may further include adding a first key to at least one of the obfuscated partitions, and adding a second key to the partition's associated randomized circuit.Type: GrantFiled: July 27, 2021Date of Patent: October 24, 2023Assignee: University of Florida Research Foundation, IncorporatedInventors: Swarup Bhunia, Abdulrahman Alaql
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Patent number: 11720654Abstract: The present disclosure provides systems and methods for timed unlocking and locking of hardware intellectual properties obfuscation. One such method includes determining whether received key inputs match a functional key sequence of an integrated circuit or a test key sequence of the integrated circuit; permanently enabling operation of the integrated circuit responsive to the received key inputs being determined to be a functional key sequence for permanently enabling operation of the integrated circuit; temporarily enabling operation of the integrated circuit responsive to the received key inputs being determined to be the test key sequence for temporarily enabling operation of the integrated circuit to perform testing of the functionality and disable thereafter; and locking sequential logic and combinational logic of the integrated circuit if the received key inputs are determined to not be either the functional key sequence or the test key sequence. Other systems and methods are also provided.Type: GrantFiled: December 13, 2021Date of Patent: August 8, 2023Assignee: University of Florida Research Foundation, Inc.Inventors: Swarup Bhunia, Abdulrahman Alaql, Aritra Dasgupta, Md Moshiur Rahman
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Patent number: 11657127Abstract: The present disclosure describes exemplary methods and systems of protecting an integrated circuit. One exemplary method comprises receiving a plurality of key inputs for enabling operation of the integrated circuit; determining whether the received key inputs are correct key inputs for enabling operation of the integrated circuit; and if the received key inputs are determined to be incorrect key inputs, locking sequential logic and combinational logic of the integrated circuit until correct key inputs are received.Type: GrantFiled: December 14, 2020Date of Patent: May 23, 2023Assignee: University of Florida Research Foundation, Inc.Inventors: Swarup Bhunia, Md Moshiur Rahman, Abdulrahman Alaql
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Publication number: 20220253563Abstract: In general, embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, and computing entities for modifying a design of a hardware IP. According to one embodiment, a method is provided, the method including generating a control and data flow graph (CDFG) representation for portions of the design. The method further includes partitioning the CDFG representation into a set of partitioned sub-graphs. The method further includes, for each partitioned sub-graph, generating a merged sub-graph to form a set of merged sub-graphs. Generating the merged sub-graph for each partitioned sub-graph involves generating a container sub-graph and merging the container sub-graph with the partitioned sub-graph to form the merged sub-graph. The container sub-graph may be a modification of the partitioned sub-graph with respect to an identified feature, in some examples.Type: ApplicationFiled: January 31, 2022Publication date: August 11, 2022Inventors: Swarup Bhunia, Abdulrahman Alaql
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Publication number: 20220222386Abstract: The present disclosure describes various embodiments of systems, apparatuses, and methods of protecting an integrated circuit. One such method comprises operating the integrated circuit under a normal mode of operation; detecting, by a decommission controller, a triggering condition for a decommission operation to be initiated for the integrated circuit; initiating, by the decommission controller, a decommission mode for the integrated circuit after detection of the triggering condition; and causing, by the decommission controller, functionality of the integrated circuit to be irreversibly disabled after initiating the decommission mode. Other methods, systems, and apparatus are also presented.Type: ApplicationFiled: January 11, 2022Publication date: July 14, 2022Inventors: Swarup BHUNIA, Md Moshiur RAHMAN, Aritra DASGUPTA, Abdulrahman ALAQL
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Publication number: 20220198108Abstract: In general, embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, computing entities, and/or the like for altering a design of a hardware intellectual property (IP). In accordance with various embodiments, a representation of the design of the hardware IP is converted to generate a control and data flow graph (CDFG) for the design. An entropy analysis of the CDFG is conducted to identify one or more control paths and/or data paths for removal. Responsive to identifying control path(s) for removal, control logic for the control path(s) is removed from the design and replaced with first reconfigurable logic. Responsive to identifying data path(s) for removal, datapath logic for the data path(s) is removed from the design and replaced with second reconfigurable logic. Logic synthesis is then performed on the design, along with verification to check functional correctness of the design of the hardware.Type: ApplicationFiled: December 15, 2021Publication date: June 23, 2022Inventors: Swarup BHUNIA, Abdulrahman ALAQL
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Publication number: 20220188387Abstract: The present disclosure provides systems and methods for timed unlocking and locking of hardware intellectual properties obfuscation. One such method includes determining whether received key inputs match a functional key sequence of an integrated circuit or a test key sequence of the integrated circuit; permanently enabling operation of the integrated circuit responsive to the received key inputs being determined to be a functional key sequence for permanently enabling operation of the integrated circuit; temporarily enabling operation of the integrated circuit responsive to the received key inputs being determined to be the test key sequence for temporarily enabling operation of the integrated circuit to perform testing of the functionality and disable thereafter; and locking sequential logic and combinational logic of the integrated circuit if the received key inputs are determined to not be either the functional key sequence or the test key sequence. Other systems and methods are also provided.Type: ApplicationFiled: December 13, 2021Publication date: June 16, 2022Inventors: Swarup Bhunia, Abdulrahman Alaql, Aritra Dasgupta, Md Moshiur Rahman
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Patent number: 11341283Abstract: Embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, and/or computing entities for obfuscating a hardware intellectual property (IP) design by locking the design based at least in part on a plurality of key-bits. In one embodiment, a method is provided comprising: generating a key vulnerability matrix for a locked version of the design and a plurality of attacks that comprises for each attack, a vector comprising a value for each key-bit identifying whether the attack successfully extracted a correct key value for the key-bit; and for each key-bit: determining whether the key-bit is vulnerable to an attack based on the values in the matrix; and responsive to being vulnerable: identifying a set of solutions to mitigate the attack; selecting a solution from the set; and inserting a key-gate type for the key-bit at a location identified by the selected solution into the design.Type: GrantFiled: November 23, 2020Date of Patent: May 24, 2022Assignee: University of Florida Research Foundation, IncorporatedInventors: Abdulrahman Alaql, Saranyu Chattopadhyay, Swarup Bhunia, Prabuddha Chakraborty
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Publication number: 20220031254Abstract: Embodiments are disclosed that enable an electronic device to instruct as user how to user one or more noninvasive sensors to measure one or more physiological parameters of a patient. In one embodiment, the measured parameters are used to obtain a diagnosis, such as a diagnosis of a critical congenital heart defect.Type: ApplicationFiled: October 19, 2021Publication date: February 3, 2022Inventors: Ammar Al-Ali, Bilal Muhsin, Omar Ahmed, Jad Adel Wafeeq, Fahad Abdulrahman Alaql, Keith Ward Indorf
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Publication number: 20220035977Abstract: A method of obfuscating a circuit design includes, in part, receiving a netlist of the circuit design, splitting the circuit design into a multitude of partitions, transforming each partitions so as to obfuscate each partition, and stitching the multitude of transformed partitions to form the obfuscated circuit. The netlist may be a register transfer level netlist. The number and the size of partitions may vary. The partitions may be distributed throughout the entirety of the design. The method may further include generating a randomized circuit associated with at least a subset of the partitions, and merging each partition with the partition's associated randomized circuit. The method may further include quantifying the amount of transformation associated with each partition. The method may further include adding a first key to at least one of the obfuscated partitions, and adding a second key to the partition's associated randomized circuit.Type: ApplicationFiled: July 27, 2021Publication date: February 3, 2022Inventors: Swarup Bhunia, Abdulrahman Alaql
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Patent number: 11172890Abstract: Embodiments are disclosed that enable an electronic device to instruct as user how to user one or more noninvasive sensors to measure one or more physiological parameters of a patient. In one embodiment, the measured parameters are used to obtain a diagnosis, such as a diagnosis of a critical congenital heart defect.Type: GrantFiled: June 14, 2019Date of Patent: November 16, 2021Assignee: Masimo CorporationInventors: Ammar Al-Ali, Bilal Muhsin, Omar Ahmed, Jad Adel Wafeeq, Fahad Abdulrahman Alaql
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Publication number: 20210192018Abstract: The present disclosure describes exemplary methods and systems of protecting an integrated circuit. One exemplary method comprises receiving a plurality of key inputs for enabling operation of the integrated circuit; determining whether the received key inputs are correct key inputs for enabling operation of the integrated circuit; and if the received key inputs are determined to be incorrect key inputs, locking sequential logic and combinational logic of the integrated circuit until correct key inputs are received.Type: ApplicationFiled: December 14, 2020Publication date: June 24, 2021Inventors: SWARUP BHUNIA, MD MOSHIUR RAHMAN, ABDULRAHMAN ALAQL
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Publication number: 20210173963Abstract: Embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, and/or computing entities for obfuscating a hardware intellectual property (IP) design by locking the design based at least in part on a plurality of key-bits. In one embodiment, a method is provided comprising: generating a key vulnerability matrix for a locked version of the design and a plurality of attacks that comprises for each attack, a vector comprising a value for each key-bit identifying whether the attack successfully extracted a correct key value for the key-bit; and for each key-bit: determining whether the key-bit is vulnerable to an attack based on the values in the matrix; and responsive to being vulnerable: identifying a set of solutions to mitigate the attack; selecting a solution from the set; and inserting a key-gate type for the key-bit at a location identified by the selected solution into the design.Type: ApplicationFiled: November 23, 2020Publication date: June 10, 2021Inventors: Abdulrahman Alaql, Saranyu Chattopadhyay, Swarup Bhunia, Prabuddha Chakraborty