Patents by Inventor Abelardo Jr. Hadap Advincula

Abelardo Jr. Hadap Advincula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9059074
    Abstract: An integrated circuit package system includes: mounting an integrated circuit die adjacent to a lead; forming a first encapsulation around and exposing the integrated circuit die and the lead; and forming a planar interconnect between the integrated circuit die and the lead with the planar interconnect on the first encapsulation.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 16, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Henry Descalzo Bathan, Abelardo Jr. Hadap Advincula
  • Patent number: 8957515
    Abstract: An integrated circuit package system includes: forming an array of external interconnects with an intersecting region between the external interconnects; removing the intersecting region for forming an isolation hole between the external interconnects; mounting an integrated circuit die over the external interconnects; connecting an internal interconnect between the integrated circuit die and the external interconnects; and forming a package encapsulation over the integrated circuit die with the external interconnects partially exposed.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: February 17, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Abelardo Jr. Hadap Advincula, Lionel Chien Hui Tay
  • Patent number: 8258614
    Abstract: An integrated circuit package system comprising: providing a substrate having a cavity; sealing a package over the cavity of the substrate; and forming an encapsulant over the package and a portion of the substrate substantially preventing the encapsulant from forming in the cavity.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: September 4, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Abelardo Jr. Hadap Advincula, Lionel Chien Hui Tay
  • Patent number: 8129827
    Abstract: An integrated circuit package system includes: forming an external interconnect; connecting an integrated circuit die and the external interconnect; forming a package encapsulation, having a recess, covering the integrated circuit die with a portion of the external interconnect exposed by the recess; and connecting an integrated circuit device and the external interconnect in the recess.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: March 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jeffrey D. Punzalan, Jairus Legaspi Pisigan, Abelardo Jr Hadap Advincula
  • Patent number: 8115287
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming outer leads having outer terminal sections, the outer terminal sections having an upper terminal and a bottom terminal; forming inner leads having inner terminal sections wider than a distance between the outer terminal sections of the outer leads, and the inner terminal sections have an upper terminal and a bottom terminal; connecting an integrated circuit to the inner leads and the outer leads; and encapsulating the integrated circuit, the inner leads, and the outer leads with an encapsulation while leaving the upper terminals and the bottom terminals of the outer terminal sections and the upper terminals and bottom terminals of the inner terminal sections exposed from the encapsulation.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: February 14, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Abelardo Jr. Hadap Advincula, Erwin Aguas Sangalang, Lionel Chien Hui Tay
  • Patent number: 8067825
    Abstract: An integrated circuit package system includes providing die; forming leads adjacent the die; forming a die paddle adjacent the leads with the die thereover; and forming a cavity for isolating one of the die and a die attach segment of the die paddle.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Abelardo Jr. Hadap Advincula, Zigmund Ramirez Camacho, Henry Descalzo Bathan, Jairus Legaspi Pisigan
  • Publication number: 20110140252
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming outer leads having outer terminal sections, the outer terminal sections having an upper terminal and a bottom terminal; forming inner leads having inner terminal sections wider than a distance between the outer terminal sections of the outer leads, and the inner terminal sections have an upper terminal and a bottom terminal; connecting an integrated circuit to the inner leads and the outer leads; and encapsulating the integrated circuit, the inner leads, and the outer leads with an encapsulation while leaving the upper terminals and the bottom terminals of the outer terminal sections and the upper terminals and bottom terminals of the inner terminal sections exposed from the encapsulation.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 16, 2011
    Inventors: Zigmund Ramirez Camacho, Abelardo Jr. Hadap Advincula, Erwin Aguas Sangalang, Lionel Chien Hui Tay
  • Patent number: 7919848
    Abstract: An integrated circuit package system includes: forming a die-attach paddle, an outer interconnect, and an inner interconnect toward the die-attach paddle beyond the outer interconnect; mounting an integrated circuit device over the die-attach paddle; connecting the integrated circuit device to the inner interconnect and the outer interconnect; encapsulating the integrated circuit device over the die-attach paddle; attaching an external interconnect under the outer interconnect; and attaching a circuit device under the die-attach paddle and extended laterally beyond opposite sides of the die-attach paddle.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: April 5, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Abelardo Jr Hadap Advincula, Lionel Chien Hui Tay
  • Patent number: 7785929
    Abstract: The present invention provides a mountable integrated circuit package system comprising: providing an inner integrated circuit package including a first external interconnect having a shoulder; connecting an intraconnect between a second external interconnect and the shoulder; and forming an outer encapsulation over the inner integrated circuit package, the intraconnect, and partially exposing the first external interconnect on a top encapsulation side of the outer encapsulation and the second external interconnect on a bottom encapsulation side of the outer encapsulation.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: August 31, 2010
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Abelardo Jr. Hadap Advincula, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Publication number: 20100140789
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an inner package so that the lead is peripheral to the inner package, and the inner package having a connection pad; forming an exposed terminal interconnect on the connection pad; and encapsulating the inner package, and partially encapsulating the exposed terminal interconnect with an encapsulation.
    Type: Application
    Filed: December 9, 2008
    Publication date: June 10, 2010
    Inventors: Arnel Senosa Trasporto, Lionel Chien Hui Tay, Zigmund Ramirez Camacho, Abelardo Jr. Hadap Advincula