Abstract: A system comprising a first layer comprising one or more metal sub-layers and a protective overcoat (PO) layer adjacent to the first layer. The PO layer is adapted to protect the first layer, and a circuit logic is at least partially embedded within the PO layer. The circuit logic couples to one of the metal sub-layers.

Abstract: A semiconductor apparatus and method are provided. According to an embodiment, the apparatus includes a first contact extending from a first conductive element disposed in a substrate. A second contact extends from a second conductive element disposed in the substrate at least to a lower limit of a capacitor well. The capacitor well is formed in a pre-metal dielectric layer disposed on the substrate. The second contact is shorter than the first contact. The height of the capacitor structure may be substantially the same as the height of the pre-metal dielectric layer. A first metal layer is disposed on the pre-metal dielectric layer. Thus, the capacitor structure may extend from the lower limit of the capacitor well to the first metal layer. The first contact extends to the first metal layer.

Abstract: A semiconductor apparatus and method are provided. According to an embodiment, the apparatus includes a first contact extending from a first conductive element disposed in a substrate. A second contact extends from a second conductive element disposed in the substrate at least to a lower limit of a capacitor well. The capacitor well is formed in a pre-metal dielectric layer disposed on the substrate. The second contact is shorter than the first contact. The height of the capacitor structure may be substantially the same as the height of the pre-metal dielectric layer. A first metal layer is disposed on the pre-metal dielectric layer. Thus, the capacitor structure may extend from the lower limit of the capacitor well to the first metal layer. The first contact extends to the first metal layer.

Abstract: A method to reduce the effective recess in conductive plugs 220 by performing an oxide etch or oxide CMP, selective to the conductive material in question. This method can be used for any conductive plug 220 (e.g. aluminum, tungsten, copper, titanium nitride, etc.). In addition, this method is also applicable in contact, via, and trench (damascene) applications. Furthermore, this process can advantageously be used in logic, SRAM, and DRAM applications.

Abstract: A method of forming a thick interlevel dielectric layer containing sealed voids, formed in a controlled manner, over a substantially planar surface in semiconductor device structure, and the semiconductor structure formed according to such a method. The sealed voids are used to reduce interlevel capacitance. A plurality of metal signal lines are formed over a globally planarized insulator. A thick layer of first conformal interlevel dielectric is deposited over the metal signal lines and over the intermetal spacings formed between the metal signal lines. Because of the thickness, flow properties, and manner of deposition of the interlevel dielectric and the aspect ratio the intermetal spacings, voids are formed in the first conformal interlevel dielectric, in the intermetal spacings. This interlevel dielectric is then etched or polished back to the desired thickness, which exposes the voids in the wider intermetal spacings, but does not expose voids in the narrower intermetal spacings.

Abstract: A method of forming a thick interlevel dielectric layer containing sealed voids formed in a controlled manner, over a substantially planar surface in semiconductor device structure, and the semiconductor structure formed according to such a method. The sealed voids are used to reduce interlevel capacitance. A plurality of metal signal lines are formed over a globally planarized insulator. A thick layer of first conformal interlevel dielectric is deposited over the metal signal lines and over the intermetal spacings formed between the metal signal lines. Because of the thickness, flow properties, and manner of deposition of the interlevel dielectric and the aspect ratio the intermetal spacings, voids are formed in the first conformal interlevel dielectric, in the intermetal spacings. This interlevel dielectric is then etched or polished back to the desired thickness, which exposes the voids in the wider intermetal spacings, but does not expose voids in the narrower intermetal spacings.

Abstract: A passivation structure is formed using two passivation layers and a protective overcoat layer using two masking steps. The first passivation layer is formed over the wafer and openings are provided to expose portions of the pads for testing the device and fusible links. After testing and laser repair, a second passivation layer is formed over the wafer followed a deposit of the protective overcoat. The protective overcoat is patterned and etched, exposing the pads. The remaining portions of the protective overcoat are used as a mask to remove portions of the second passivation layer overlying the pads. Leads are then attached to pads and the devices are encapsulated for packaging. The second passivation layer overlaps edge portions of the first passivation layer at the bond pads to enhance moisture resistance.