Abstract: A validating service of a plurality of services that compose an application receives a security token that identifies an entity that has submitted a transaction to the application, the security token indicating that the entity is authorized to submit the transaction to the application. The validating service obtains a transaction identifier that uniquely identifies the transaction. The validating service sends, to a collector service, the transaction identifier and data derived from the security token that identifies the entity. A downstream service receives input data associated with the transaction, the input data including the transaction identifier. The downstream service accesses an information source to obtain information. The downstream service sends, to the collector service, the transaction identifier and metadata about the information.

Abstract: A receiving apparatus includes a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus may be coupled through a resistance to a common node of the terminating network. The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

Abstract: A receiving apparatus includes a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus may be coupled through a resistance to a common node of the terminating network. The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

Abstract: Implementations described herein relate to systems and methods to provide platform agnostic query acceleration. In some implementations, a method includes receiving, at a processor associated with a query acceleration service, a request from an client/application, wherein the request conforms to a particular wire protocol of a plurality of supported wire protocols, and wherein the request includes header data and body content data, analyzing the request to identify at least one of a query and a command in the body content data, determining an optimal matched model of the one or more query acceleration models, rewriting the query based on the optimal matched model, transmitting the rewritten query to the query processing platform, receiving a response to the rewritten query or the query from the query processing platform, and transmitting the received response to the application, wherein the transmission is configured based on the particular wire protocol.

Abstract: Methods, apparatus, and systems for clock and data recovery in a C-PHY interface are disclosed. A receiving device has a plurality of differential receivers and a recovery circuit. The differential receivers are configured to generate difference signals. Each difference signal is representative of voltage difference between one pair of wires in a three-wire serial bus. The recovery circuit is configured to identify a first difference signal that has the greatest voltage magnitude among the plurality of difference signals in a first unit interval and determine signaling state of the three-wire serial bus for the first unit interval based on identity of the pair of wires corresponding to the first difference signal and polarity of the first difference signal in the first unit interval, and to generate a first edge in a clock signal responsive to a transition in the first difference signal during the first unit interval.

Abstract: In certain aspects, a device comprises one or more IO inputs; a first receiver coupled to a first supply voltage and the one or more IO inputs, wherein the first receiver comprises thick oxide transistors; and a high-speed circuit comprising: an isolation block coupled to the one or more IO inputs, wherein the isolation block comprises thick oxide transistors; and a second receiver coupled to the isolation block and a second supply voltage, wherein the second receiver comprises thin oxide transistors.

Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery apparatus has a plurality of pulse generating circuits, a logic circuit and a delay flipflop. Each pulse generating circuit generates transition pulses in response to transitions in one of three difference signals representative of a difference in signaling state of a pair of wires in a three-wire bus. Transitions in the difference signals can occur at boundaries between sequentially-transmitted symbols. The first logic circuit may provide a single pulse in a combination signal at each boundary between pairs of symbols by combining one or more transition pulses. The delay flipflop is configured to respond to each pulse in the combination signal by changing signaling state of a clock signal that is output by the clock recovery apparatus. The symbols may be sequentially transmitted over the three-wire bus in accordance with a C-PHY protocol.

Abstract: Methods, apparatus, and systems for communication over a multi-wire, multiphase interface are disclosed. A clock recovery apparatus has a plurality of pulse generating circuits, a logic circuit and a delay flipflop. Each pulse generating circuit generates transition pulses in response to transitions in one of three difference signals representative of a difference in signaling state of a pair of wires in a three-wire bus. Transitions in the difference signals can occur at boundaries between sequentially-transmitted symbols. The first logic circuit may provide a single pulse in a combination signal at each boundary between pairs of symbols by combining one or more transition pulses. The delay flipflop is configured to respond to each pulse in the combination signal by changing signaling state of a clock signal that is output by the clock recovery apparatus. The symbols may be sequentially transmitted over the three-wire bus in accordance with a C-PHY protocol.

Abstract: In certain aspects, a device comprises one or more IO inputs; a first receiver coupled to a first supply voltage and the one or more IO inputs, wherein the first receiver comprises thick oxide transistors; and a high-speed circuit comprising: an isolation block coupled to the one or more IO inputs, wherein the isolation block comprises thick oxide transistors; and a second receiver coupled to the isolation block and a second supply voltage, wherein the second receiver comprises thin oxide transistors.

Abstract: Duty cycle correction circuits are provided that include a serial combination of a first inverter and a second inverter for inverting an input clock signal into an output clock signal having a corrected duty cycle. The duty cycle correction circuits also include a serial combination of a third inverter and a fourth inverter for inverting a complement input clock signal into a complement output clock signal having a corrected duty cycle.

Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of calibration includes configuring a 3-phase signal to include a high frequency component and a low frequency component during a calibration period, and transmitting a version of the 3-phase signal on each wire of a 3-wire interface. The version of the 3-phase signal transmitted on each wire is out-of-phase with the versions of the 3-phase signal transmitted on each of the other wires of the 3-wire interface. The 3-phase signal may be configured to enable a receiver to determine certain operating parameters of the 3-wire interface.

Abstract: Methods, apparatus, and systems for calibration and correction of data communications over a multi-wire, multi-phase interface are disclosed. In particular, calibration is provided for data communication devices coupled to a 3-line interface. The calibration includes generating and transmitting a calibration pattern on the 3-line interface, where the generation of the pattern includes toggling two of three interface lines from one voltage level to another voltage level over a predetermined time interval. Furthermore, the generation of the pattern includes maintaining a remaining third interface line at a common mode voltage level over the predetermined time interval, wherein only a single transition occurs for the predetermined time interval. Calibration data may then be derived in a receiver device using the transmitted calibration pattern.

Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.

Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.

Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of calibration includes configuring a 3-phase signal to include a high frequency component and a low frequency component during a calibration period, and transmitting a version of the 3-phase signal on each wire of a 3-wire interface. The version of the 3-phase signal transmitted on each wire is out-of-phase with the versions of the 3-phase signal transmitted on each of the other wires of the 3-wire interface. The 3-phase signal may be configured to enable a receiver to determine certain operating parameters of the 3-wire interface.

Abstract: The present invention relates to a protection method based on preplanning duality of paths for a unicast and/or a multicast traffic, by extending a network into hierarchy of connected rings to form a hierarchical ring based tree (HRBT) structure. The present method enables a deterministic method to route a frame (or packet) when a primary path to destination is unavailable due to node/link failure, bandwidth crunch, mis-configuration, etc. If both primary and secondary (or alternate) path are pre-provisioned before traffic is allowed, the switch-over time from primary (P) path to secondary (S) path will be minimized, thus enabling 50 ms protection switching in packet network.

Abstract: A monopod mounted solid pet waste collecting and disposing system, is a pole device with a mounted scooper box. When not in use, the scooper box is mounted vertically parallel to the walking stick. When required for pet waste collection, it is deployed horizontally parallel to the ground. The Scooper box has a provision to insert a specially designed disposable case inside the box which has lower lips to protect the surface of scooper box coming in contact with pet waste and side lips that allows the case to be opened or closed in sync with the scooper box. The internal section of the stick also has control systems to deploy the scooper box for pet waste pick-up, to open and close the two compartments of the scooper box to collect the pet waste from ground and to eject the disposable case out of scooper box.

Abstract: A monopod mounted solid pet waste collecting and disposing system, hereafter referred to as the “Pooper Scooper” is a pole device with a mounted scooper box. When not in use, the scooper box is mounted vertically parallel to the walking stick. When required for pet waste collection, it is deployed towards the horizontally parallel to the ground. The internal section of the stick has a mechanism that opens and closes the two segments of the scooper box. The Scooper box has a provision to insert a specially designed disposable cup or case inside the box which not only collects the pet waste, its distinctive design also protects the surfaces of the scooper box from coming in contact with the waste. The lower lip protects the lower edge of the scooper box from coming in contact with any waste or rough surfaces. Each disposable case also has an outer lip that allows the case to be opened or closed in sync with the scooper box.

Abstract: The present invention relates to a protection method based on preplanning duality of paths for a unicast and/or a multicast traffic, by extending a network into hierarchy of connected rings to form a hierarchical ring based tree (HRBT) structure. The present method enables a deterministic method to route a frame (or packet) when a primary path to destination is unavailable due to node/link failure, bandwidth crunch, mis-configuration, etc. If both primary and secondary (or alternate) path are pre-provisioned before traffic is allowed, the switch-over time from primary (P) path to secondary (S) path will be minimized, thus enabling 50 ms protection switching in packet network.

Abstract: An electronic device is described. The electronic device includes a first integrated circuit (IC) and a second integrated circuit (IC). The electronic device also includes a multiplexer configured to multiplex a parallel data signal into a serial data signal, and a transmitter configured to transmit the serial data signal from the first IC to the second IC. The electronic device further includes a receiver configured to receive the serial data signal. The receiver includes a clamp circuit configured to clamp the voltage swing of an analog node within a determined range. The clamp also helps to extend the bandwidth of the receiver.