Abstract: Apparatus and method for power management and especially to power management integrated circuits (PMICs). In one aspect, the invention relates to a PMIC having an internal non-volatile memory (NVM) for storing boot settings for the PMIC. The PMIC also has control circuitry for detecting whether a source of boot settings is available, such as an NVM external to the PMIC, and, if so, using any settings stored in the external source in preference to the relevant settings stored in the internal NVM. The external settings can thus override any internal settings, which is useful for fault diagnosis and/or development. In one aspect the PMIC may have programming circuitry for automatically programming boot settings from an external source into the internal NVM.

Abstract: Apparatus and method for power management and especially to power management integrated circuits (PMICs). In one aspect, the invention relates to a PMIC having an internal non-volatile memory (NVM) for storing boot settings for the PMIC. The PMIC also has control circuitry for detecting whether a source of boot settings is available, such as an NVM external to the PMIC, and, if so, using any settings stored in the external source in preference to the relevant settings stored in the internal NVM. The external settings can thus override any internal settings, which is useful for fault diagnosis and/or development. In one aspect the PMIC may have programming circuitry for automatically programming boot settings from an external source into the internal NVM.

Abstract: An integrated circuit combination, comprising first and second integrated circuit dies with respective first and second control register banks, and a path for external control data, within said combination, coupling a first data interface on said first die, which receives the external control data, to the first and second control register banks.

Abstract: A circuit for debouncing a signal from a switch or other input. The invention provides an arrangement which receives an input signal and which monitors the input to provide an output which switches after a predetermined time from the input signal changing from one state to another. However, the output changes back to its original state in a much shorter time if said input changes back to its original state.

Abstract: An integrated circuit comprises a system clock and an interface clock. A synchronizing circuit is provided for synchronizing a control signal associated with a predetermined command, for example a PENABLE signal associated with a WRITE command, when the system clock of the integrated circuit is present and bypassing the synchronization circuitry when the system clock is not present. Thus, whenever the system clock of the integrated circuit is active, all the control interface write operations are synchronized to the system clock, and hence there are no timing issues due to different clock domains. If the system clock is not present, the asynchronous writes cannot cause any timing problems, and the synchronization circuit is therefore bypassed.

Abstract: A circuit for debouncing a signal from a switch or other input. The invention provides an arrangement which receives an input signal and which monitors the input to provide an output which switches after a predetermined time from the input signal changing from one state to another. However, the output changes back to its original state in a much shorter time if said input changes back to its original state.