Patents by Inventor Abhay Ramrao Deshmukh

Abhay Ramrao Deshmukh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7585784
    Abstract: A system and method is disclosed for reducing etch sequencing induced downstream dielectric defects produced in a SOG planarization process used in high volume semiconductor manufacturing. Three factors have been identified as causes of the defects. The three factors are: (1) phosphorus-doping in the base dielectric, and (2) using for SOG etchback an etch tool that was last used for a bond pad etch process, and (3) residual metal contaminants in the etch chamber used for the SOG etchback. Elimination of any one of these three factors eliminates the defects.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: September 8, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Abhay Ramrao Deshmukh, Satnam Singh Doad
  • Patent number: 7358611
    Abstract: A system and method is disclosed for adjusting the ratio of deposition times to optimize via density and via fill in an aluminum multilayer metallization process during a manufacturing process of a semiconductor wafer. In a two-step cold/hot aluminum sputtering process via fill becomes more challenging as via density increases. The invention increases the percentage of successful via fills by changing the ratio of the cold/hot deposition times. Denser via structures require extended cold deposition times to compensate for higher via density. The percentage of successful via fills was increased from forty percent (40%) to seventy percent (70%) by changing the ratio of the cold/hot deposition times from 60:40 to 79:21.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: April 15, 2008
    Assignee: National Semiconductor Corporation
    Inventor: Abhay Ramrao Deshmukh
  • Patent number: 7230517
    Abstract: A system and method is disclosed for using plasma to adjust the resistance of a thin film resistor. In one advantageous embodiment of the invention, the resistance of a thin film resistor is increased to cause the thin film resistor to have a desired higher value of resistance. The thin film resistor is formed having an initial value of resistance that is less than the desired value of resistance. Then the thin film resistor is placed in an oxidizing atmosphere. A surface of the thin film resistor is then oxidized to increase the initial value of resistance to the desired value of resistance. The amount of the increase in resistance may be selected by selecting the temperature of the oxidizing atmosphere.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: June 12, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Richard Wendell Foote, Jr., Tom Bold, Rodney Hill, Abhay Ramrao Deshmukh
  • Patent number: 7189645
    Abstract: A system and method is disclosed for adjusting the ratio of deposition times to optimize via density and via fill in an aluminum multilayer metallization process during a manufacturing process of a semiconductor wafer. In a two-step cold/hot aluminum sputtering process via fill becomes more challenging as via density increases. The invention increases the percentage of successful via fills by changing the ratio of the cold/hot deposition times. Denser via structures require extended cold deposition times to compensate for higher via density. The percentage of successful via fills was increased from forty percent (40%) to seventy percent (70%) by changing the ratio of the cold/hot deposition times from 60:40 to 79:21.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: March 13, 2007
    Assignee: National Semiconductor Corporation
    Inventor: Abhay Ramrao Deshmukh