Abstract: Systems and methods for estimating power consumption in a network of computing devices are described. Operational information of a target server is periodically received and compared to benchmark data of a model of the target server. The operational information comprises performance data of the target server during a predefined time interval. Power consumption of the target server is estimated using the performance and benchmark data. The benchmark data is recalibrated if an error in the estimated power consumption is detected. An agent installed on the target server for collecting performance data is described. The target server can be a virtualized server, in which case, the agent acquires at least some of the performance data from a hypervisor of a physical server that hosts the target server.

Abstract: Systems and methods for estimating power consumption in a network of computing devices are described. Operational information of a target server is periodically received and compared to benchmark data of a model of the target server. The operational information comprises performance data of the target server during a predefined time interval. Power consumption of the target server is estimated using the performance and benchmark data. The benchmark data is recalibrated if an error in the estimated power consumption is detected. An agent installed on the target server for collecting performance data is described. The target server can be a virtualized server, in which case, the agent acquires at least some of the performance data from a hypervisor of a physical server that hosts the target server.

Abstract: This invention relates to a method and processor (19) for power analysis in digital circuits. The method incorporates a main processor (19) and an associative memory mechanism (101a, 101b, 102, 104, 105, 106), the associative memory mechanism comprising a plurality of associative arrays (101a, 101b), an input value register (102), at least one result register (104) and a memory block area (29). A circuit design is transformed into a functionally equivalent model format suitable for processing in the associative array and thereafter input vectors are applied to the circuit and a record is kept of the inputs and or the outputs on each of the gates in the circuit over a specified time period. In this way, it is possible to calculate the leakage power dissipation as well as both the toggle dynamic power and the transition dynamic power.