Abstract: The present invention provides mixed metal oxide-hydroxide biopolymer composite beads for fluoride removal from groundwater and a process for the preparation thereof. The beads developed in the instant invention relate to novel granular adsorption medium which comprises two or more metal oxide-hydroxide/hydroxide/oxide nanoparticles and calcium alginate as supporting medium. The said mixed metal oxide-hydroxides and biopolymer composite (MBC) beads are useful for the treatment of fluoride containing drinking water by both batch and continuous mode operations. The MBC beads also showed arsenic sorption performance from spiked water by batch mode.

Abstract: Samples of a light radar (“LIDAR”) return signal are stored in an analog circular buffer following the transmission of a LIDAR pulse. Sampling continues for a fixed period of time or number of samples during a post-trigger sampling period after the occurrence of a trigger signal from a trigger circuit. The trigger circuit indicates the receipt of a return pulse associated with a target object based upon one or more return signal characteristics. Following the post-trigger sampling period, the stored analog samples are sequentially read out and converted to digital sample values. The digital sample values may be analyzed in a digital processor to further confirm the validity of the returned LIDAR pulse, to determine a time of arrival of the LIDAR pulse, and to calculate a distance to the target object. Some versions include multiple circular buffers and capture clocks, enabling the capture of samples from multiple return pulses.

Abstract: Samples of a light radar (“LIDAR”) return signal are stored in an analog circular buffer following the transmission of a LIDAR pulse. Sampling continues for a fixed period of time or number of samples during a post-trigger sampling period after the occurrence of a trigger signal from a trigger circuit. The trigger circuit indicates the receipt of a return pulse associated with a target object based upon one or more return signal characteristics. Following the post-trigger sampling period, the stored analog samples are sequentially read out and converted to digital sample values. The digital sample values may be analyzed in a digital processor to further confirm the validity of the returned LIDAR pulse, to determine a time of arrival of the LIDAR pulse, and to calculate a distance to the target object. Some versions include multiple circular buffers and capture clocks, enabling the capture of samples from multiple return pulses.

Abstract: An integrated wafer processing system and a method thereof is disclosed. In one embodiment, a wafer stack of sliced wafers includes a base, and a plurality of sliced wafers extending outwardly from the base, where the plurality of sliced wafers are obtained by slicing a portion of a work piece, where the base is an uncut portion which is the remaining portion of the work piece or a plate attached by welding to the plurality of sliced wafers and where the work piece is mono-crystalline or multi-crystalline silicon. Further, the wafer stack of sliced wafers are treated in-situ in cleaning and wet chemical tanks for processes such as damage etching, texturization and oxide etching and also treated in-situ in high temperature furnaces for processes such as diffusion and anti-reflection coating.

Abstract: A method and apparatus of cutting and cleaning wafers in a wire saw is disclosed. In one embodiment, a wire sawing apparatus includes a horizontal ingot feeding wire slicing apparatus which includes a vertical wire web, in which sawing wires of the vertical wire web are located substantially in a vertical plane and move in a substantially vertical direction, a first top outlet and a second top outlet located in a top position with respect to a work piece for applying fluids during sawing, and at least one chute located substantially below the work piece for receiving the fluids, wherein the work piece is impelled against the vertical wire web by horizontal movement and the fluids flow in a vertical direction against and into the work piece for slicing and cleaning wafers.

Abstract: Abrasive grain powder, in particular intended for machining silicon ingots, such that the granulometric fraction D40-D60 comprises more than 15% and less than 80%, as percentages by volume, of grains having circularity of less than 0.85.

Abstract: Abrasive grain powder, in particular intended for machining silicon ingots, such that the granulometric fraction D40-D60 comprises more than 15% and less than 80%, as percentages by volume, of grains having circularity of less than 0.85.

Abstract: A fully differential amplifier circuit provided according to an aspect of the present invention contains a stabilization block to measure the common mode component at the output of an input stage, and to inject a current proportionate to the common mode component into each of a pair of paths forming the output of the input stage to stabilize a feedback loop formed by the input stage, an output stage and a common mode feedback block. In an embodiment, the stabilization block contains a buffer to receive the measured common mode component and to provide a buffered output. The injected current is generated based on the buffered output. Due to the presence of the buffer, the differential loop may not be affected by injection of the additional current, thereby avoiding any distortions in the output signal.

Abstract: A method and apparatus of cutting and cleaning wafers in a wire saw is disclosed. In one embodiment, a wire sawing apparatus includes a horizontal ingot feeding wire slicing apparatus which includes a vertical wire web, in which sawing wires of the vertical wire web are located substantially in a vertical plane and move in a substantially vertical direction, a first top outlet and a second top outlet located in a top position with respect to a work piece for applying fluids during sawing, and at least one chute located substantially below the work piece for receiving the fluids, wherein the work piece is impelled against the vertical wire web by horizontal movement and the fluids flow in a vertical direction against and into the work piece for slicing and cleaning wafers.

Abstract: A method and apparatus of cutting wafers by wire sawing is disclosed. In one embodiment, a wire sawing apparatus includes a horizontal ingot feeding wire slicing apparatus which includes a vertical wire web, in which sawing wires of the vertical wire web are located substantially in a vertical plane and move in a substantially vertical direction, a top outlet located in top position with respect to a work piece for applying fluid during sawing, and a chute located substantially below the work piece for receiving the fluid, wherein the work piece is impelled against the vertical wire web by horizontal movement and the fluid moves in a vertical direction against and into the work piece. The wire sawing apparatus further includes a frame for holding the horizontal ingot feeding wire slicing apparatus, and a control panel for operating the wire sawing apparatus.

Abstract: An integrated wafer processing system and a method thereof is disclosed. In one embodiment, a wafer stack of sliced wafers includes a base, and a plurality of sliced wafers extending outwardly from the base, where the plurality of sliced wafers are obtained by slicing a portion of a work piece, where the base is an uncut portion which is the remaining portion of the work piece or a plate attached by welding to the plurality of sliced wafers and where the work piece is mono-crystalline or multi-crystalline silicon. Further, the wafer stack of sliced wafers are treated in-situ in cleaning and wet chemical tanks for processes such as damage etching, texturization and oxide etching and also treated in-situ in high temperature furnaces for processes such as diffusion and anti-reflection coating.

Abstract: A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one capacitor of a pair is connected to a positive reference voltage, and the other capacitor is connected to a negative reference voltage if the input signal exceeds a corresponding threshold voltage. When the input signal does not exceed the corresponding threshold voltage, both capacitors of the pair are connected either to the positive or the negative reference voltage. As a result, the need for a common mode reference voltage may be eliminated, and the residue block can be implemented with a smaller area.

Abstract: A voltage source providing a constant reference voltage, independent of load variations at an output terminal. The effective impedance (looking-in impedance) at the output terminal is designed to be independent of frequency of the signals at the output terminal. In an embodiment, the resistance of one of two parallel impedance paths constituting the effective impedance is made equal to the resistance of the other path, and the time constants of both paths are made equal. As a result, the effective impedance is made independent of frequency, and the strength of the reference voltage is maintained constant without exhibiting ringing, DC droop, etc., despite load variations.

Abstract: A voltage source providing a constant reference voltage, independent of load variations at an output terminal. The effective impedance (looking-in impedance) at the output terminal is designed to be independent of frequency of the signals at the output terminal. In an embodiment, the resistance of one of two parallel impedance paths constituting the effective impedance is made equal to the resistance of the other path, and the time constants of both paths are made equal. As a result, the effective impedance is made independent of frequency, and the strength of the reference voltage is maintained constant without exhibiting ringing, DC droop, etc., despite load variations.

Abstract: A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one capacitor of a pair is connected to a positive reference voltage, and the other capacitor is connected to a negative reference voltage if the input signal exceeds a corresponding threshold voltage. When the input signal does not exceed the corresponding threshold voltage, both capacitors of the pair are connected either to the positive or the negative reference voltage. As a result, the need for a common mode reference voltage may be eliminated, and the residue block can be implemented with a smaller area.

Abstract: A flash ADC in which different thresholds are provided to different comparators in different time instances. Such a feature may be advantageously used in digital converters type components since the flash ADC would provide more time for amplifiers to generate amplified residue signals.

Abstract: Removing an Nth harmonic (of a fundamental frequency) generated due to non-ideal ADC operation from the output of the ADC. In an embodiment, digital values containing in-phase and quadrature phase components of the Nth harmonic are generated using mathematical operations, scaled using scaling factors, and then subtracted from the (non-ideal) output of the ADC. A continuous-time derivative of the input signal used to generate the quadrature phase component, enabling a same set of scaling factors to be used for the same input irrespective of the sampling frequency. Spurious Free Dynamic Range of the ADC is thus improved.

Abstract: A fully differential amplifier circuit provided according to an aspect of the present invention contains a stabilization block to measure the common mode component at the output of an input stage, and to inject a current proportionate to the common mode component into each of a pair of paths forming the output of the input stage to stabilize a feedback loop formed by the input stage, an output stage and a common mode feedback block. In an embodiment, the stabilization block contains a buffer to receive the measured common mode component and to provide a buffered output. The injected current is generated based on the buffered output. Due to the presence of the buffer, the differential loop may not be affected by injection of the additional current, thereby avoiding any distortions in the output signal.

Abstract: A comparator presents a linear load to input signals when providing a comparison output of two input signals. The comparator contains a transistor configured in a source/emitter follower configuration, and operates in the saturation region for substantially the entire range of strengths of the input signals. As a result, the comparator presents a substantially constant load to the input signals. When incorporated in circuits such as a pipeline ADC, the comparator may substantially eliminate errors due to non-linear loads.

Abstract: A delay locked loop (DLL) circuit in which situations of lock to multiple periods of a reference signal is determined by a lock detector using dummy delay elements and a duty cycle correction circuit (DCC). The lock detector, the dummy delay elements and the delay control circuit are used in a path parallel to the delay elements which generate the desired delayed signals having different delays in relation to the reference signal. Due to the use of the parallel path, the throughput performance of the DLL circuit is not impeded. In an embodiment, separate charge pumps are used by a phase comparator and the lock detector used in the parallel path.