Patents by Inventor Abhaya Kumar
Abhaya Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240370287Abstract: Computer implemented methods, systems, and computer program products include program code executing on a processor(s) that ingests data from one or more computing environments, where the data is related to applications. The processor(s) identifies, based on utilizing topic modeling and latent semantic analysis of the data, homogenous applications among the applications, which include analyzing subdata handled by each application and functionalities of each application; the homogenous applications comprise similarities in the data and in the functionalities. The processor(s) determines overlapping data among the homogenous applications based on the topic modeling, the latent semantic analysis, and term frequency-inverse document frequency of terms in the overlapping data. The processor(s) selects, from the overlapping data, training data. The processor(s) utilizes the training data to calculate weights for disposition metrics and the metrics to predict the resource dispositions for the applications.Type: ApplicationFiled: May 4, 2023Publication date: November 7, 2024Inventors: Pranshu Tiwari, Swarnalata Patel, Saurabh Trehan, Harish Bharti, Abhaya Kumar Sahoo
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Publication number: 20240241707Abstract: In various examples, a computer-implemented method includes: ingesting, by one or more computing devices, application deployment data for an application; generating, by the one or more computing devices, a cloud application deployment predictor data structure for the application; generating, by the one or more computing devices, objective functions for the cloud application deployment predictor data structure for the application; optimizing, by the one or more computing devices, between the objective functions for the application; and generating, by the one or more computing devices, based on the optimizing between the objective functions, a multi-cloud deployment map for the application.Type: ApplicationFiled: January 12, 2023Publication date: July 18, 2024Inventors: PRANSHU TIWARI, Harish Bharti, Swarnalata Patel, NAVEEN NARAYANASWAMY, Abhaya Kumar Sahoo
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Publication number: 20230415121Abstract: The present invention provides mixed metal oxide-hydroxide biopolymer composite beads for fluoride removal from groundwater and a process for the preparation thereof. The beads developed in the instant invention relate to novel granular adsorption medium which comprises two or more metal oxide-hydroxide/hydroxide/oxide nanoparticles and calcium alginate as supporting medium. The said mixed metal oxide-hydroxides and biopolymer composite (MBC) beads are useful for the treatment of fluoride containing drinking water by both batch and continuous mode operations. The MBC beads also showed arsenic sorption performance from spiked water by batch mode.Type: ApplicationFiled: August 4, 2022Publication date: December 28, 2023Inventors: Sujana MARYGUDE, Sathish RAMALINGAM, Boopathy RAMASAMY, Abhaya KUMAR SAHOO, Biswaranjan DAS, Priyankarani BEHERA, Debabrata SINGH, Suddhasatwa BASU
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Patent number: 9684066Abstract: Samples of a light radar (“LIDAR”) return signal are stored in an analog circular buffer following the transmission of a LIDAR pulse. Sampling continues for a fixed period of time or number of samples during a post-trigger sampling period after the occurrence of a trigger signal from a trigger circuit. The trigger circuit indicates the receipt of a return pulse associated with a target object based upon one or more return signal characteristics. Following the post-trigger sampling period, the stored analog samples are sequentially read out and converted to digital sample values. The digital sample values may be analyzed in a digital processor to further confirm the validity of the returned LIDAR pulse, to determine a time of arrival of the LIDAR pulse, and to calculate a distance to the target object. Some versions include multiple circular buffers and capture clocks, enabling the capture of samples from multiple return pulses.Type: GrantFiled: October 20, 2014Date of Patent: June 20, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Eduardo Bartolome, Fernando Alberto Mujica, Sandeep Oswal, Abhaya Kumar
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Publication number: 20150116695Abstract: Samples of a light radar (“LIDAR”) return signal are stored in an analog circular buffer following the transmission of a LIDAR pulse. Sampling continues for a fixed period of time or number of samples during a post-trigger sampling period after the occurrence of a trigger signal from a trigger circuit. The trigger circuit indicates the receipt of a return pulse associated with a target object based upon one or more return signal characteristics. Following the post-trigger sampling period, the stored analog samples are sequentially read out and converted to digital sample values. The digital sample values may be analyzed in a digital processor to further confirm the validity of the returned LIDAR pulse, to determine a time of arrival of the LIDAR pulse, and to calculate a distance to the target object. Some versions include multiple circular buffers and capture clocks, enabling the capture of samples from multiple return pulses.Type: ApplicationFiled: October 20, 2014Publication date: April 30, 2015Inventors: Eduardo Bartolome, Fernando Alberto Mujica, Sandeep Oswal, Abhaya Kumar
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Patent number: 8261730Abstract: An integrated wafer processing system and a method thereof is disclosed. In one embodiment, a wafer stack of sliced wafers includes a base, and a plurality of sliced wafers extending outwardly from the base, where the plurality of sliced wafers are obtained by slicing a portion of a work piece, where the base is an uncut portion which is the remaining portion of the work piece or a plate attached by welding to the plurality of sliced wafers and where the work piece is mono-crystalline or multi-crystalline silicon. Further, the wafer stack of sliced wafers are treated in-situ in cleaning and wet chemical tanks for processes such as damage etching, texturization and oxide etching and also treated in-situ in high temperature furnaces for processes such as diffusion and anti-reflection coating.Type: GrantFiled: January 28, 2009Date of Patent: September 11, 2012Assignee: Cambridge Energy Resources IncInventors: Abhaya Kumar Bakshi, Bhaskar Chandra Panigrahi
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Patent number: 8065995Abstract: A method and apparatus of cutting and cleaning wafers in a wire saw is disclosed. In one embodiment, a wire sawing apparatus includes a horizontal ingot feeding wire slicing apparatus which includes a vertical wire web, in which sawing wires of the vertical wire web are located substantially in a vertical plane and move in a substantially vertical direction, a first top outlet and a second top outlet located in a top position with respect to a work piece for applying fluids during sawing, and at least one chute located substantially below the work piece for receiving the fluids, wherein the work piece is impelled against the vertical wire web by horizontal movement and the fluids flow in a vertical direction against and into the work piece for slicing and cleaning wafers.Type: GrantFiled: January 13, 2009Date of Patent: November 29, 2011Assignee: Cambridge Energy Resources IncInventors: Abhaya Kumar Bakshi, Bhaskar Chandra Panigrahi
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Patent number: 8002861Abstract: Abrasive grain powder, in particular intended for machining silicon ingots, such that the granulometric fraction D40-D60 comprises more than 15% and less than 80%, as percentages by volume, of grains having circularity of less than 0.85.Type: GrantFiled: February 6, 2009Date of Patent: August 23, 2011Assignee: Saint-Gobain Centre de Recherches et d'Etudes EuropeanInventors: Yves Boussant-Roux, Jostein Mosby, Ana-Maria Popa, Arne Menne, Abhaya Kumar Bakshi
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Publication number: 20110100346Abstract: Abrasive grain powder, in particular intended for machining silicon ingots, such that the granulometric fraction D40-D60 comprises more than 15% and less than 80%, as percentages by volume, of grains having circularity of less than 0.85.Type: ApplicationFiled: February 6, 2009Publication date: May 5, 2011Inventors: Yves Boussant-Roux, Jostein Mosby, Ana-Maria Popa, Arne Menne, Abhaya Kumar Bakshi
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Patent number: 7750737Abstract: A fully differential amplifier circuit provided according to an aspect of the present invention contains a stabilization block to measure the common mode component at the output of an input stage, and to inject a current proportionate to the common mode component into each of a pair of paths forming the output of the input stage to stabilize a feedback loop formed by the input stage, an output stage and a common mode feedback block. In an embodiment, the stabilization block contains a buffer to receive the measured common mode component and to provide a buffered output. The injected current is generated based on the buffered output. Due to the presence of the buffer, the differential loop may not be affected by injection of the additional current, thereby avoiding any distortions in the output signal.Type: GrantFiled: August 22, 2008Date of Patent: July 6, 2010Assignee: Texas Instruments IncorporatedInventors: Raghu Srinivasa, Visvesvaraya Appala Pentakota, Abhaya Kumar
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Publication number: 20100126488Abstract: A method and apparatus of cutting wafers by wire sawing is disclosed. In one embodiment, a wire sawing apparatus includes a horizontal ingot feeding wire slicing apparatus which includes a vertical wire web, in which sawing wires of the vertical wire web are located substantially in a vertical plane and move in a substantially vertical direction, a top outlet located in top position with respect to a work piece for applying fluid during sawing, and a chute located substantially below the work piece for receiving the fluid, wherein the work piece is impelled against the vertical wire web by horizontal movement and the fluid moves in a vertical direction against and into the work piece. The wire sawing apparatus further includes a frame for holding the horizontal ingot feeding wire slicing apparatus, and a control panel for operating the wire sawing apparatus.Type: ApplicationFiled: December 24, 2008Publication date: May 27, 2010Inventors: Abhaya Kumar Bakshi, Bhaskar Chandra Panigrahi
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Publication number: 20100126490Abstract: A method and apparatus of cutting and cleaning wafers in a wire saw is disclosed. In one embodiment, a wire sawing apparatus includes a horizontal ingot feeding wire slicing apparatus which includes a vertical wire web, in which sawing wires of the vertical wire web are located substantially in a vertical plane and move in a substantially vertical direction, a first top outlet and a second top outlet located in a top position with respect to a work piece for applying fluids during sawing, and at least one chute located substantially below the work piece for receiving the fluids, wherein the work piece is impelled against the vertical wire web by horizontal movement and the fluids flow in a vertical direction against and into the work piece for slicing and cleaning wafers.Type: ApplicationFiled: January 13, 2009Publication date: May 27, 2010Inventors: ABHAYA KUMAR BAKSHI, Bhaskar Chandra Panigrahi
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Publication number: 20100126489Abstract: An integrated wafer processing system and a method thereof is disclosed. In one embodiment, a wafer stack of sliced wafers includes a base, and a plurality of sliced wafers extending outwardly from the base, where the plurality of sliced wafers are obtained by slicing a portion of a work piece, where the base is an uncut portion which is the remaining portion of the work piece or a plate attached by welding to the plurality of sliced wafers and where the work piece is mono-crystalline or multi-crystalline silicon. Further, the wafer stack of sliced wafers are treated in-situ in cleaning and wet chemical tanks for processes such as damage etching, texturization and oxide etching and also treated in-situ in high temperature furnaces for processes such as diffusion and anti-reflection coating.Type: ApplicationFiled: January 28, 2009Publication date: May 27, 2010Inventors: Abhaya Kumar Bakshi, Bhaskar Chandra Panigrahi
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Patent number: 7579975Abstract: A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one capacitor of a pair is connected to a positive reference voltage, and the other capacitor is connected to a negative reference voltage if the input signal exceeds a corresponding threshold voltage. When the input signal does not exceed the corresponding threshold voltage, both capacitors of the pair are connected either to the positive or the negative reference voltage. As a result, the need for a common mode reference voltage may be eliminated, and the residue block can be implemented with a smaller area.Type: GrantFiled: December 11, 2007Date of Patent: August 25, 2009Assignee: Texas Instruments IncorporatedInventors: Sandeep Mallya Perdoor, Abhaya Kumar, Shakti Shankar Rath
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Patent number: 7573414Abstract: A voltage source providing a constant reference voltage, independent of load variations at an output terminal. The effective impedance (looking-in impedance) at the output terminal is designed to be independent of frequency of the signals at the output terminal. In an embodiment, the resistance of one of two parallel impedance paths constituting the effective impedance is made equal to the resistance of the other path, and the time constants of both paths are made equal. As a result, the effective impedance is made independent of frequency, and the strength of the reference voltage is maintained constant without exhibiting ringing, DC droop, etc., despite load variations.Type: GrantFiled: December 6, 2007Date of Patent: August 11, 2009Assignee: Texas Instruments IncorporatedInventors: Abhaya Kumar, Visvesvarya Pentakota, Nitin Agarwal, Jagannathan Venkataraman
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Publication number: 20090146857Abstract: A voltage source providing a constant reference voltage, independent of load variations at an output terminal. The effective impedance (looking-in impedance) at the output terminal is designed to be independent of frequency of the signals at the output terminal. In an embodiment, the resistance of one of two parallel impedance paths constituting the effective impedance is made equal to the resistance of the other path, and the time constants of both paths are made equal. As a result, the effective impedance is made independent of frequency, and the strength of the reference voltage is maintained constant without exhibiting ringing, DC droop, etc., despite load variations.Type: ApplicationFiled: December 6, 2007Publication date: June 11, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Abhaya Kumar, Visvesvarya Pentakota A, Nitin Agarwal, Jagannathan Venkataraman
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Publication number: 20090146855Abstract: A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one capacitor of a pair is connected to a positive reference voltage, and the other capacitor is connected to a negative reference voltage if the input signal exceeds a corresponding threshold voltage. When the input signal does not exceed the corresponding threshold voltage, both capacitors of the pair are connected either to the positive or the negative reference voltage. As a result, the need for a common mode reference voltage may be eliminated, and the residue block can be implemented with a smaller area.Type: ApplicationFiled: December 11, 2007Publication date: June 11, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Sandeep Mallya Perdoor, Abhaya Kumar, Shakti Shankar Rath
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Publication number: 20090091483Abstract: A flash ADC in which different thresholds are provided to different comparators in different time instances. Such a feature may be advantageously used in digital converters type components since the flash ADC would provide more time for amplifiers to generate amplified residue signals.Type: ApplicationFiled: October 4, 2007Publication date: April 9, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jagannathan Venkataraman, Abhaya Kumar
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Publication number: 20090091487Abstract: Removing an Nth harmonic (of a fundamental frequency) generated due to non-ideal ADC operation from the output of the ADC. In an embodiment, digital values containing in-phase and quadrature phase components of the Nth harmonic are generated using mathematical operations, scaled using scaling factors, and then subtracted from the (non-ideal) output of the ADC. A continuous-time derivative of the input signal used to generate the quadrature phase component, enabling a same set of scaling factors to be used for the same input irrespective of the sampling frequency. Spurious Free Dynamic Range of the ADC is thus improved.Type: ApplicationFiled: October 4, 2007Publication date: April 9, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Nagarajan Viswanathan, Nitin Agarwal, Jagannathan Venkataraman, Visvesvaraya Pentakota, Abhaya Kumar
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Publication number: 20090058527Abstract: A fully differential amplifier circuit provided according to an aspect of the present invention contains a stabilization block to measure the common mode component at the output of an input stage, and to inject a current proportionate to the common mode component into each of a pair of paths forming the output of the input stage to stabilize a feedback loop formed by the input stage, an output stage and a common mode feedback block. In an embodiment, the stabilization block contains a buffer to receive the measured common mode component and to provide a buffered output. The injected current is generated based on the buffered output. Due to the presence of the buffer, the differential loop may not be affected by injection of the additional current, thereby avoiding any distortions in the output signal.Type: ApplicationFiled: August 22, 2008Publication date: March 5, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Raghu Srinivasa, Visvesvaraya Appala Pentakota, Abhaya Kumar