Abstract: A voltage clamp is disclosed. The voltage clamp may include a plurality of transistors to limit the voltage between a power supply and ground. In addition, the voltage clamp may include a positive feedback signal to reduce turn-on time of the plurality of transistors.

Abstract: A voltage clamp is disclosed. The voltage clamp may include a plurality of transistors to limit the voltage between a power supply and ground. In addition, the voltage clamp may include a positive feedback signal to reduce turn-on time of the plurality of transistors.

Abstract: Embodiments of disclosure generally relate to integrated circuits (ICs) and, more particularly, a voltage-triggered edge-insensitive electrostatic discharge (ESD) clamp for protection of ICs. An example trigger circuit is provided for controlling a current shunt in an IC. The trigger circuit generally includes a comparison circuit configured to compare a monitored voltage to a reference voltage and output a signal indicating when the monitored voltage reaches or exceeds the reference voltage; and a shunt circuit configured to shunt the current based on receiving the signal from the comparison circuit. The voltage-triggered edge-insensitive clamp provides a single protection circuit that protects against all types of ESD and/or electrostatic overstress (EOS) events.

Abstract: Embodiments of disclosure generally relate to integrated circuits (ICs) and, more particularly, a voltage-triggered edge-insensitive electrostatic discharge (ESD) clamp for protection of ICs. An example trigger circuit is provided for controlling a current shunt in an IC. The trigger circuit generally includes a comparison circuit configured to compare a monitored voltage to a reference voltage and output a signal indicating when the monitored voltage reaches or exceeds the reference voltage; and a shunt circuit configured to shunt the current based on receiving the signal from the comparison circuit. The voltage-triggered edge-insensitive clamp provides a single protection circuit that protects against all types of ESD and/or electrostatic overstress (EOS) events.

Abstract: A device for providing electrostatic discharge (ESD) protection includes circuitry configured to detect an occurrence of an ESD event at one or more voltage rails. An ESD clamp is activated via a clamp triggering path to provide a discharge path for an ESD current. A gate voltage of the ESD clamp is maintained greater than a predetermined threshold via a holding path in parallel with the clamp triggering path.

Abstract: An electrostatic discharge (ESD) clamp, coupled across input-output (I/O) and common (GND) terminals of a protected semiconductor device or integrated circuit is provided. One ESD clamp comprises an ESD transistor (ESDT) with source-drain coupled between the GND and I/O terminals, a first resistor coupled between the gate and source and a second resistor coupled between the ESDT body and source. Paralleling the resistors are control transistors with gates coupled to one or more bias supplies Vb, Vb?. The main power rail (Vdd) of the device or IC is a convenient source for Vb, Vb?. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

Abstract: An electrostatic discharge (ESD) clamp, coupled across input-output (I/O) and common (GND) terminals of a protected semiconductor device or integrated circuit is provided. One ESD clamp comprises an ESD transistor (ESDT) with source-drain coupled between the GND and I/O terminals, a first resistor coupled between the gate and source and a second resistor coupled between the ESDT body and source. Paralleling the resistors are control transistors with gates coupled to one or more bias supplies Vb, Vb?. The main power rail (Vdd) of the device or IC is a convenient source for Vb, Vb?. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

Abstract: An electrostatic discharge (ESD) clamp (41, 51, 61, 71, 81, 91), coupled across input-output (I/O) (22) and common (GND) (23) terminals of a protected semiconductor SC device or IC (24), comprises, an ESD transistor (ESDT) (25) with source-drain (26, 27) coupled between the GND (23) and I/O (22), a first resistor (30) coupled between gate (28) and source (26) and a second resistor (30) coupled between ESDT body (29) and source (26). Paralleling the resistors (30, 32) are control transistors (35, 35?) with gates (38, 38?) coupled to one or more bias supplies Vb, Vb?. The main power rail (Vdd) of the device or IC (24) is a convenient source for Vb, Vb?. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

Abstract: Methods for sensing and building sensors provide for adding nanotubes to a sensor to improve characteristics such as the Q-factor associated with the sensor. Mass loading and damping characteristics of micromachined quartz crystal resonators on which a thin film of debundled single-walled carbon nanotube (SWNT) has been deposited are disclosed. An absolute mass sensitivity of ˜100 fg was experimentally measured by monitoring the continuous desorption of gases from SWNT surfaces in a vacuum ambient.

Abstract: An electrostatic discharge (ESD) protection device (61, 71), coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, multiple serially coupled ESD clamp stages (41, 41?), each stage (41, 41?) comprising an interior node (52, 52?) and first (32, 32?) and second terminal (42, 42?) nodes wherein the first terminal node (42) of the first clamp stage (41) is coupled to the common terminal (23) and the second terminal node (42?) of the last clamp stages (41?) is coupled to the I/O terminals (22). A resistance-capacitance ladder (60) is provided in parallel with some of the clamp stages (41, 41?), with a resistance (R1, R2, R3 etc.) coupled to each of the nodes (32, 52, 65 (42; 32?)) of one of the ESD clamp stages (41, 41?) by first terminals thereof and capacitors (C1, C2, etc.) are coupled between second terminals of the resistances (R1, R2, R3 etc.).

Abstract: An electrostatic discharge (ESD) clamp (41, 51, 61, 71, 81, 91), coupled across input-output (I/O) (22) and common (GND) (23) terminals of a protected semiconductor SC device or IC (24), comprises, an ESD transistor (ESDT) (25) with source-drain (26, 27) coupled between the GND (23) and I/O (22), a first resistor (30) coupled between gate (28) and source (26) and a second resistor (30) coupled between ESDT body (29) and source (26). Paralleling the resistors (30, 32) are control transistors (35, 35?) with gates (38, 38?) coupled to one or more bias supplies Vb, Vb?. The main power rail (Vdd) of the device or IC (24) is a convenient source for Vb, Vb?. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

Abstract: An electrostatic discharge (ESD) protection device (61, 71), coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, multiple serially coupled ESD clamp stages (41, 41?), each stage (41, 41?) comprising an interior node (52, 52?) and first (32, 32?) and second terminal (42, 42?) nodes wherein the first terminal node (42) of the first clamp stage (41) is coupled to the common terminal (23) and the second terminal node (42?) of the last clamp stages (41?) is coupled to the I/O terminals (22). A resistance-capacitance ladder (60) is provided in parallel with some of the clamp stages (41, 41?), with a resistance (R1, R2, R3 etc.) coupled to each of the nodes (32, 52, 65 (42; 32?)) of one of the ESD clamp stages (41, 41?) by first terminals thereof and capacitors (C1, C2, etc.) are coupled between second terminals of the resistances (R1, R2, R3 etc.).

Abstract: Methods for sensing and building sensors provide for adding nanotubes to a sensor to improve characteristics such as the Q-factor associated with the sensor. Mass loading and damping characteristics of micromachined quartz crystal resonators on which a thin film of debundled single-walled carbon nanotube (SWNT) has been deposited are disclosed. An absolute mass sensitivity of ˜100 fg was experimentally measured by monitoring the continuous desorption of gases from SWNT surfaces in a vacuum ambient.