Patents by Inventor Abhijat Ranade

Abhijat Ranade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11687435
    Abstract: A processing unit can include a performance monitor for monitoring the performance of the processing unit and associated sub-units. The performance monitor can include a state machine. The state machine can be implemented via state machine data entries stored in a memory associated with the performance monitor. A state machine data entry includes information indicating a state transition condition and output signals. The state transition condition includes a current state and input signals required to meet the condition. The output signals include a next state, one or more counter actions, and one or more triggers. The performance monitor implements logic circuits that determine, based on input signals and the state machine data entries, the next state to transition and associated output signals. The state machine data entries can be written and re-written by a user.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: June 27, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Gongyu Zhou, Shounak Kamalapurkar, Yogesh Kulkarni, Thomas Melvin Ogletree, Abhijat Ranade
  • Patent number: 11144087
    Abstract: Performance monitors are placed on computational units in different clock domains of an integrated circuit. A central dispatcher generates trigger signals to the performance monitors to cause the performance monitors to respond to the trigger signals with packets reporting local performance counts for the associated computational units. The data in the packets are correlated into a single clock domain. By applying a trigger and reporting system, the disclosed approach can synchronize the performance metrics of the various computational units in the different clock domains without having to route a complex global clock reference signal to all of the performance monitors.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 12, 2021
    Assignee: NVIDIA Corporation
    Inventors: Roger Allen, Alan Menezes, Tom Ogletree, Shounak Kamalapurkar, Abhijat Ranade
  • Publication number: 20200050482
    Abstract: Performance monitors are placed on computational units in different clock domains of an integrated circuit. A central dispatcher generates trigger signals to the performance monitors to cause the performance monitors to respond to the trigger signals with packets reporting local performance counts for the associated computational units. The data in the packets are correlated into a single clock domain. By applying a trigger and reporting system, the disclosed approach can synchronize the performance metrics of the various computational units in the different clock domains without having to route a complex global clock reference signal to all of the performance monitors.
    Type: Application
    Filed: March 12, 2019
    Publication date: February 13, 2020
    Inventors: Roger Allen, Alan Menezes, Tom Ogletree, Shounak Kamalapurkar, Abhijat Ranade