Patents by Inventor Abhijeet Kolpekwar
Abhijeet Kolpekwar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230315964Abstract: A computing system implementing a design verification system can classify a mixed-signal circuit design describing an electronic device based on a design topology of the mixed-signal circuit design. This classification can be performed by identifying a top-level design block in the mixed-signal circuit design, traversing a connectivity of a design hierarchy to identify lower-level design blocks in the mixed-signal circuit design, and classifying the mixed-signal circuit design based on at least one of a design type of the top-level design block, design types of the lower-level design blocks, or a connectivity of design blocks in the mixed-signal circuit design. The design verification system can selectively partition the mixed-signal circuit design into an analog partition and a digital partition based on the classification, and simulate the analog partition of the mixed-signal circuit design with an analog simulator and the digital partition of the mixed-signal circuit design with a digital simulator.Type: ApplicationFiled: August 25, 2020Publication date: October 5, 2023Applicant: Siemens Industry Software Inc.Inventors: Abhijeet Kolpekwar, Kingshuk Banerjee
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Patent number: 9058440Abstract: Disclosed are methods, systems, and structures for implementing an improved approach for simulating mixed-signal electronic circuits with specialized power management requirements, such as low power designs. Some approaches provide an improved method and system for providing a highly reliable, usable and scalable solution to allow for designers to use their power information files in a mixed-signal simulation and carry the impact of power intents defined on the digital blocks onto the analog blocks without needing any manual changes to models/designs.Type: GrantFiled: December 15, 2009Date of Patent: June 16, 2015Assignee: Cadence Design Systems, Inc.Inventor: Abhijeet Kolpekwar
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Patent number: 8640073Abstract: For increasing user control and insight into preparing a mixed semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignments of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.Type: GrantFiled: May 20, 2013Date of Patent: January 28, 2014Assignee: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Iyengar Srinivasan
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Publication number: 20130326440Abstract: For increasing user control and insight into preparing a mixed semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignments of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.Type: ApplicationFiled: May 20, 2013Publication date: December 5, 2013Applicant: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Srinivasan Iyengar
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Patent number: 8504346Abstract: Disclosed are methods, systems, and structures for implementing an improved approach for simulating mixed-signal electronic designs. An improved approach for providing seamless interaction between analog and digital blocks during simulation, even if the digital blocks include complex types or models.Type: GrantFiled: December 15, 2009Date of Patent: August 6, 2013Assignee: Cadence Design Systems, Inc.Inventors: Abhijeet Kolpekwar, Chandrashekar L. Chetput
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Patent number: 8448116Abstract: For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.Type: GrantFiled: August 31, 2010Date of Patent: May 21, 2013Assignee: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Srinivasan Iyengar
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Patent number: 8296699Abstract: A system, method, and computer program product is disclosed for utilizing dual-value signals, such as hierarchical dual-value signals, for mixed-signal simulation. Such dual-value signals can hold both analog and digital representations of a signal and use the appropriate representations based on which block (analog or digital) for which there is an interaction.Type: GrantFiled: February 26, 2010Date of Patent: October 23, 2012Assignee: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar
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Patent number: 8255191Abstract: A method is provided to coerce a wire type net in an integrated circuit design to become a wreal net in the design, comprising: running a wreal coercion process on a computer system including the acts of, identifying a wire type net that is connected to a wreal net in an integrated circuit design; and converting the identified wire type net to a wreal net.Type: GrantFiled: April 30, 2009Date of Patent: August 28, 2012Assignee: Cadence Design Systems, Inc.Inventors: Abhijeet Kolpekwar, Chandrashekar L. Chetput, Timothy Martin O'Leary
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Patent number: 8234617Abstract: A system, method, and computer program product is disclosed that recycle digital assertions for mixed-signal electronic designs. The approach enables the re-use of pure digital assertions which reference signals that turn out to resolve to analog due to the particular circuit configuration chosen during the verification process.Type: GrantFiled: October 1, 2009Date of Patent: July 31, 2012Assignee: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Donald J. O'Riordan
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Patent number: 7979262Abstract: Connections between digital blocks and other circuit components, such as power supplies and clocks, are verified using a discrete property or object, such as a discrete discipline. A discrete discipline is defined for each value of an operating parameter, such as voltage or clock speed, that is used in a circuit design. Each discrete discipline is propagated throughout respective nets using bottom-up and/or top-down propagation. As a result, each digital net is associated with a power supply value through its corresponding discrete discipline. A determination is made whether two digital nets are connected to each other within the same digital island. If so, a determination is made whether the digital nets are compatible. If they have conflicting discrete disciplines, then they are not compatible and an error report or signal can be generated to identify the incompatibility and its location. Compatibility checks can disregard grounded digital nets.Type: GrantFiled: March 9, 2006Date of Patent: July 12, 2011Assignee: Cadence Design Systems, Inc.Inventors: Srinivasan Iyengar, Abhijeet Kolpekwar, Chandrashekar L. Chetput
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Publication number: 20110083114Abstract: A system, method, and computer program product is disclosed that recycle digital assertions for mixed-signal electronic designs. The approach enables the re-use of pure digital assertions which reference signals that turn out to resolve to analog due to the particular circuit configuration chosen during the verification process.Type: ApplicationFiled: October 1, 2009Publication date: April 7, 2011Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Chandrashekar L. CHETPUT, Abhijeet KOLPEKWAR, Donald J. O'RIORDAN
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Publication number: 20100333050Abstract: For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.Type: ApplicationFiled: August 31, 2010Publication date: December 30, 2010Applicant: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Srinivasan Iyengar
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Patent number: 7797659Abstract: For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.Type: GrantFiled: January 29, 2007Date of Patent: September 14, 2010Assignee: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Srinivasan Iyengar
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Patent number: 7523424Abstract: System and method for representing analog connectivity in a design written in a hardware description language are disclosed. The method includes detecting a circuit component that does not have explicit connection path in the design, where the circuit component includes one or more lower-level circuit instances arranged in one or more branches in a hierarchical graph. The method further includes creating one or more instances of the circuit component having at least one additional port than the circuit component, creating one or more ports in the corresponding one or more instances of the circuit component for providing at least an explicit connection path, and representing the design using at least the explicit connection path and the one or more ports of the corresponding one or more instances.Type: GrantFiled: November 30, 2005Date of Patent: April 21, 2009Assignee: Cadence Design Systems, Inc.Inventors: Abhijeet Kolpekwar, Scott Cranston, Peter Frey
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Publication number: 20080184181Abstract: For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.Type: ApplicationFiled: January 29, 2007Publication date: July 31, 2008Applicant: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Srinivasan Iyengar
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Patent number: 7251795Abstract: A method for connecting Verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design includes receiving a mixed-language mixed-signal design, where the mixed-language mixed-signal design comprises one or more VHDL-AMS and Verilog-AMS components, including a first VHDL-AMS component and a first Verilog-AMS component. The method further includes receiving a predetermined set of connection rules, resolving incompatibilities between the first VHDL-AMS component and the first Verilog-AMS component in accordance with the predetermined set of connection rules, and connecting the first VHDL-AMS component to the first Verilog-AMS component.Type: GrantFiled: September 27, 2004Date of Patent: July 31, 2007Assignee: Cadence Design Systems, Inc.Inventors: Prasenjit Biswas, Ramesh S. Mayiladuthurai, Chandrashekar L. Chetput, Abhijeet Kolpekwar
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Publication number: 20070124706Abstract: System and method for representing analog connectivity in a design written in a hardware description language are disclosed. The method includes detecting a circuit component that does not have explicit connection path in the design, where the circuit component includes one or more lower-level circuit instances arranged in one or more branches in a hierarchical graph. The method further includes creating one or more instances of the circuit component having at least one additional port than the circuit component, creating one or more ports in the corresponding one or more instances of the circuit component for providing at least an explicit connection path, and representing the design using at least the explicit connection path and the one or more ports of the corresponding one or more instances.Type: ApplicationFiled: November 30, 2005Publication date: May 31, 2007Applicant: Cadence Design Systems, Inc.Inventors: Abhijeet Kolpekwar, Scott Cranston, Peter Frey
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Publication number: 20060074626Abstract: A method for connecting Verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design includes receiving a mixed-language mixed-signal design, where the mixed-language mixed-signal design comprises one or more VHDL-AMS and Verilog-AMS components, including a first VHDL-AMS component and a first Verilog-AMS component. The method further includes receiving a predetermined set of connection rules, resolving incompatibilities between the first VHDL-AMS component and the first Verilog-AMS component in accordance with the predetermined set of connection rules, and connecting the first VHDL-AMS component to the first Verilog-AMS component.Type: ApplicationFiled: September 27, 2004Publication date: April 6, 2006Applicant: Cadence Design Systems, Inc.Inventors: Prasenjit Biswas, Ramesh Mayiladuthurai, Chandrashekar Chetput, Abhijeet Kolpekwar