Patents by Inventor Abhijeet S. Bagal
Abhijeet S. Bagal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12198928Abstract: Exemplary semiconductor processing methods may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may define one or more recessed features. The methods may include providing a second precursor to the processing region. The methods may include forming a plasma of the carbon-containing precursor and the second precursor in the processing region. Forming the plasma of the carbon-containing precursor and the second precursor may be performed at a plasma power of greater than or about 500 W. The methods may include depositing a carbon-containing material on the substrate. The carbon-containing material may extend within the one or more recessed features. The methods may include, subsequent depositing the carbon-containing material for a first period of time, applying a bias power while depositing the carbon-containing material for a second period of time.Type: GrantFiled: October 22, 2021Date of Patent: January 14, 2025Assignee: Applied Materials, Inc.Inventors: Abhijeet S. Bagal, Qian Fu
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Publication number: 20240420948Abstract: Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature less than or about 4 eV is generated from the deposition gas. The methods further include depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, where the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1. Also described are semiconductor structures that include an as-deposited carbon-containing layer on the top and bottom surface of at least a first and second trench, where the carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1.Type: ApplicationFiled: August 27, 2024Publication date: December 19, 2024Applicant: Applied Materials, Inc.Inventors: Abhijeet S. Bagal, Qian Fu, Kuan-Ting Liu, Chung Liu
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Publication number: 20240404837Abstract: Methods of semiconductor processing may include providing a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed on a substrate support within the processing region. A layer of silicon-and-nitrogen-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the hydrogen-containing precursor. The methods may include contacting the layer of silicon-and-nitrogen-containing material with plasma effluents of the hydrogen-containing precursor. The contacting may etch a portion of the layer of silicon-and-nitrogen-containing material.Type: ApplicationFiled: May 30, 2023Publication date: December 5, 2024Applicant: Applied Materials, Inc.Inventors: Zhiren Luo, Jeong Hwan Kim, Qian Fu, Abhijeet S. Bagal
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Patent number: 12125699Abstract: Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature less than or about 4 eV is generated from the deposition gas. The methods further include depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, where the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1. Also described are semiconductor structures that include an as-deposited carbon-containing layer on the top and bottom surface of at least a first and second trench, where the carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1.Type: GrantFiled: June 28, 2021Date of Patent: October 22, 2024Assignee: Applied Materials, Inc.Inventors: Abhijeet S. Bagal, Qian Fu, Kuan-Ting Liu, Chung Liu
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Publication number: 20240210995Abstract: A display may have a stretchable portion with hermetically sealed rigid pixel islands. A flexible interconnect region may be interposed between the hermetically sealed rigid pixel islands. The hermetically sealed rigid pixel islands may include organic light-emitting diode (OLED) pixels. A conductive cutting structure may have an undercut that causes a discontinuity in a conductive OLED layer to mitigate lateral leakage. The conductive cutting structure may also be electrically connected to a cathode for the OLED pixels and provide a cathode voltage to the cathode. First and second inorganic passivation layers may be formed over the OLED pixels. Multiple discrete portions of an organic inkjet printed layer may be interposed between the first and second inorganic passivation layers.Type: ApplicationFiled: October 10, 2023Publication date: June 27, 2024Inventors: Prashant Mandlik, Bhadrinarayana Lalgudi Visweswaran, Mahendra Chhabra, Chia-Hao Chang, Shiyi Liu, Siddharth Harikrishna Mohan, Zhen Zhang, Han-Chieh Chang, Yi Qiao, Yue Cui, Tyler R Kakuda, Michael Vosgueritchian, Sudirukkuge T. Jinasundera, Warren S Rieutort-Louis, Tsung-Ting Tsai, Jae Won Choi, Jiun-Jye Chang, Jean-Pierre S Guillou, Rui Liu, Po-Chun Yeh, Chieh Hung Yang, Ankit Mahajan, Takahide Ishii, Pei-Ling Lin, Pei Yin, Gwanwoo Park, Markus Einzinger, Martijn Kuik, Abhijeet S Bagal, Kyounghwan Kim, Jonathan H Beck, Chiang-Jen Hsiao, Chih-Hao Kung, Chih-Lei Chen, Chih-Yu Chung, Chuan-Jung Lin, Jung Yen Huang, Kuan-Chi Chen, Shinya Ono, Wei Jung Hsieh, Wei-Chieh Lin, Yi-Pu Chen, Yuan Ming Chiang, An-Di Sheu, Chi-Wei Chou, Chin-Fu Lee, Ko-Wei Chen, Kuan-Yi Lee, Weixin Li, Shin-Hung Yeh, Shyuan Yang, Themistoklis Afentakis, Asli Sirman, Baolin Tian, Han Liu
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Publication number: 20230129550Abstract: Exemplary semiconductor processing methods may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may define one or more recessed features. The methods may include providing a second precursor to the processing region. The methods may include forming a plasma of the carbon-containing precursor and the second precursor in the processing region. Forming the plasma of the carbon-containing precursor and the second precursor may be performed at a plasma power of greater than or about 500 W. The methods may include depositing a carbon-containing material on the substrate. The carbon-containing material may extend within the one or more recessed features. The methods may include, subsequent depositing the carbon-containing material for a first period of time, applying a bias power while depositing the carbon-containing material for a second period of time.Type: ApplicationFiled: October 22, 2021Publication date: April 27, 2023Applicant: Applied Materials, Inc.Inventors: Abhijeet S. Bagal, Qian Fu
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Publication number: 20220415648Abstract: Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature less than or about 4 eV is generated from the deposition gas. The methods further include depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, where the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1. Also described are semiconductor structures that include an as-deposited carbon-containing layer on the top and bottom surface of at least a first and second trench, where the carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1.Type: ApplicationFiled: June 28, 2021Publication date: December 29, 2022Applicant: Applied Materials, Inc.Inventors: Abhijeet S. Bagal, Qian Fu, Kuan-Ting Liu, Chung Liu
