Patents by Inventor Abhijeet SAMUDRA

Abhijeet SAMUDRA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12140632
    Abstract: Systems, integrated circuits and methods for synchronizing testing a Device under test (DUT) with an automated test equipment (ATE) is provided. In one example, a method includes transmitting a test packet from an ATE to a first Device Under Test DUT; receiving, at the ATE from the DUT, a result packet; and in response to receiving a Start of Packet (SOP) indicator from the DUT at the ATE, evaluating the first DUT by comparing the result packet to an expected packet associated with the test packet.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: November 12, 2024
    Assignee: Synopsys, Inc.
    Inventors: Yongkang Hu, Ramalingam Kolisetti, Anubhav Sinha, Abhijeet Samudra
  • Patent number: 11860751
    Abstract: Test packets may be received at a design under test (DUT) from an automated test equipment (ATE) over a serializer/deserializer (SERDES) connection between the ATE and the DUT. The test packets may include test pattern data to test the DUT. The test pattern data may be applied to the DUT using a set of scan chains and test response data corresponding to the test pattern data may be obtained. The test response data may be received by a circuit in the DUT at irregular time intervals. Response packets may be sent to the ATE by the circuit in the DUT at regular time intervals, where the response packets may include a portion of the test response data (which may be encoded using an encoding technique), and where the response packets may be sent to ATE over the SERDES connection.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: January 2, 2024
    Assignee: Synopsys, Inc.
    Inventors: Abhijeet Samudra, Ajay Nagarandal, Anubhav Sinha, Luis M. Cruz, Milin Kaushik Raijada, Ramalingam Kolisetti, Naresh Thakur, Saransh Nagaich, Jatin Verma
  • Patent number: 11662383
    Abstract: An integrated circuit (IC) device and a method for communicating test data utilizes test control circuitry, and a test controller. The test controller is coupled with the test control circuitry and decodes packetized test pattern data to identify configuration data for the test controller and test data for the test control circuitry. The test controller further communicates the test data to the test control circuitry, and packetizes resulting data received from the test control circuitry. The resulting data corresponds to errors identified by a test performed based on the test pattern data.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: May 30, 2023
    Assignee: Synopsys, Inc.
    Inventors: Anubhav Sinha, Brian Archer, Abhijeet Samudra, Kranthi Kandula, Amit Kapatkar, Akshay Kumar Gupta, Hemasagar Babu Reddy, Ajay Nagarandal
  • Publication number: 20220155370
    Abstract: Systems, integrated circuits and methods for synchronizing testing a Device under test (DUT) with an automated test equipment (ATE) is provided. In one example, a method includes transmitting a test packet from an ATE to a first Device Under Test DUT; receiving, at the ATE from the DUT, a result packet; and in response to receiving a Start of Packet (SOP) indicator from the DUT at the ATE, evaluating the first DUT by comparing the result packet to an expected packet associated with the test packet.
    Type: Application
    Filed: November 17, 2021
    Publication date: May 19, 2022
    Inventors: Yongkang HU, Ramalingam KOLISETTI, Anubhav SINHA, Abhijeet SAMUDRA
  • Publication number: 20220120811
    Abstract: An integrated circuit (IC) device and a method for communicating test data utilizes test control circuitry, and a test controller. The test controller is coupled with the test control circuitry and decodes packetized test pattern data to identify configuration data for the test controller and test data for the test control circuitry. The test controller further communicates the test data to the test control circuitry, and packetizes resulting data received from the test control circuitry. The resulting data corresponds to errors identified by a test performed based on the test pattern data.
    Type: Application
    Filed: October 14, 2021
    Publication date: April 21, 2022
    Inventors: Anubhav SINHA, Brian ARCHER, Abhijeet SAMUDRA, Kranthi KANDULA, Amit KAPATKAR, Akshay Kumar GUPTA, Hemasagar BABU REDDY, Ajay NAGARANDAL