Abstract: An optical sensor package capable of being surface mounted, and in a form that enables multiple packages to be fabricated simultaneously and then array tested in a wafer stack prior to singulation. The package comprises a chip carrier, a device chip electrically and mechanically connected to a first surface of the chip carrier with solder connections, and a capping chip secured to the chip carrier to hermetically enclose the device chip. The device chip has an optical sensing element on a surface thereof, while the capping chip has means for enabling radiation to pass therethrough to the device chip. The chip carrier includes conductive vias that are electrically connected to the solder connections of the device chip and extend through the chip carrier to bond pads on a second surface of the chip carrier, enabling the package to be surface mounted with solder connections to a suitable substrate.

Abstract: A process using integrated sensor technology in which a micromachined sensing element and signal processing circuit are combined on a single semiconductor substrate to form, for example, an infrared sensor. The process is based on modifying a CMOS process to produce an improved layered micromachined member, such as a diaphragm, after the circuit fabrication process is completed. The process generally entails forming a circuit device on a substrate by processing steps that include forming multiple dielectric layers and at least one conductive layer on the substrate. The dielectric layers comprise an oxide layer on a surface of the substrate and at least two dielectric layers that are in tension, with the conductive layer being located between the two dielectric layers. The surface of the substrate is then dry etched to form a cavity and delineate the diaphragm and a frame surrounding the diaphragm.

Abstract: An integrated sensor comprising a thermopile transducer and signal processing circuitry that are combined on a single semiconductor substrate, such that the transducer output signal is sampled in close vicinity by the processing circuitry. The sensor comprises a frame formed of a semiconductor material that is not heavily doped, and with which a diaphragm is supported. The diaphragm has a first surface for receiving thermal (e.g., infrared) radiation, and comprises multiple layers that include a sensing layer containing at least a pair of interlaced thermopiles. Each thermopile comprises a sequence of thermocouples, each thermocouple comprising dissimilar electrically-resistive materials that define hot junctions located on the diaphragm and cold junctions located on the frame. The signal processing circuitry is located on the frame and electrically interconnected with the thermopiles.

Abstract: A semiconductor device (20) comprises a substrate (24), a first semiconductor region including a recessed area defining a first cavity (36) between the substrate (24) and the first semiconductor region, an electrical transducer (30) positioned within the first cavity (36), a second semiconductor.region including a recessed area defining a second cavity (40) between the substrate (24) and the second semiconductor region, an electrical circuit (34) positioned within the second cavity (40), and at least one electrode connecting the electrical transducer (30) and the electrical device (34). The semiconductor device (20) includes a first external electrode and a second external electrode formed on the substrate (24) and a sealing layer extending around the perimeter of the cavities and sealing the semiconductor regions to the substrate (24). The sealing layer (78) includes a first electrical connection region and a second electrical connection region that are electrically isolated from each other.

Abstract: An integrated sensor comprising a thermopile transducer and signal processing circuitry that are combined on a single semiconductor substrate, such that the transducer output signal is sampled in close vicinity by the processing circuitry. The sensor comprises a frame formed of a semiconductor material that is not heavily doped, and with which a diaphragm is supported. The diaphragm has a first surface for receiving thermal (e.g., infrared) radiation, and comprises multiple layers that include a sensing layer containing at least a pair of interlaced thermopiles. Each thermopile comprises a sequence of thermocouples, each thermocouple comprising dissimilar electrically-resistive materials that define hot junctions located on the diaphragm and cold junctions located on the frame. The signal processing circuitry is located on the frame and electrically interconnected with the thermopiles.

Abstract: An optical sensor package capable of being surface mounted, and in a form that enables multiple packages to be fabricated simultaneously and then array tested in a wafer stack prior to singulation. The package comprises a chip carrier, a device chip electrically and mechanically connected to a first surface of the chip carrier with solder connections, and a capping chip secured to the chip carrier to hermetically enclose the device chip. The device chip has an optical sensing element on a surface thereof, while the capping chip has means for enabling radiation to pass therethrough to the device chip. The chip carrier includes conductive vias that are electrically connected to the solder connections of the device chip and extend through the chip carrier to bond pads on a second surface of the chip carrier, enabling the package to be surface mounted with solder connections to a suitable substrate.

Abstract: A process using integrated sensor technology in which a micromachined sensing element and signal processing circuit are combined on a single semiconductor substrate to form, for example, an infrared sensor. The process is based on modifying a CMOS process to produce an improved layered micromachined member, such as a diaphragm, after the circuit fabrication process is completed. The process generally entails forming a circuit device on a substrate by processing steps that include forming multiple dielectric layers and at least one conductive layer on the substrate. The dielectric layers comprise an oxide layer on a surface of the substrate and at least two dielectric layers that are in tension, with the conductive layer being located between the two dielectric layers. The surface of the substrate is then dry etched to form a cavity and delineate the diaphragm and a frame surrounding the diaphragm.

Abstract: A non-linear temperature compensation circuit (10) is provided for generating at least dual-slope characteristics responsive to changes in operating temperature of the compensation circuit. The compensation circuit includes a temperature dependent current generator circuit (11) for generating at least one output (I4) substantially proportional to changes in the temperature of the circuit, a current-based dual-slope drift generator (12) for generating a current proportional to absolute temperature, and a summing means (14) for summing both current outputs and generating a compensation drift voltage. The temperature dependent current generator includes a sub-circuit having a first current generator that generates a current (I2) that is relatively independent of temperature, and a second current generator that generates a second current (I3) that decreases with increases in temperature.

Abstract: A capacitive pressure sensor that uses polysilicon as an electrostatic bonding medium and as a lead transfer to make an electrical connection to an electrode within a vacuum sealed chamber. The heavily doped P++ region of a silicon wafer defines a movable diaphragm that is bonded to a glass substrate of the sensor. The diaphragm is one electrode of the capacitor and includes a recess that defines the sealed chamber. An internal electrode is patterned on the glass substrate in the sealed chamber, and is the other electrode of the capacitor. An internal lead within the chamber is electrically connected to the internal electrode and a polysilicon layer that seals the diaphragm electrode to the glass substrate. Dielectric isolation layers are provided to electrically isolate the polysilicon sealing layer in the diaphragm electrode, and isolate the polysilicon sealing layer from an etchant that removes a polysilicon region around the diaphragm electrode during fabrication.

Abstract: A semiconductor device that uses polysilicon as an electrostatic bonding medium and as a lead transfer for multiple lead connection to one or more electrical devices within a vacuum sealed chamber. A semiconductor region, such as a heavily built P++ silicon region, is bonded to a glass substrate of the device. The semiconductor region includes a recess that defines a chamber between the semiconductor region and the substrate. Multiple internal electrodes or lead transfers within the chamber pass through separate electrical connection regions in a polysilicon sealing layer that seals the semiconductor region to the substrate. In one embodiment, each of the separate electrical connection regions includes an upper polysilicon region and a lower polysilicon region separated by a dielectric layer. The lower polysilicon region includes a first separate polysilicon region electrically connected to one of the internal leads and a second separate polysilicon region electrically connected to an external lead.

Abstract: A noise tolerant motor position monitoring circuit having a digital filter section receives and filters noisy hall effect sensor inputs for use in determining rotational motor position. The motor position monitoring circuit exchanges information and instructions with a microprocessor which utilizes the motor position information to calculate motor distance traveled, motor speed, etc. The hall effect sensor signals are noisy due to the particular environment in which the sensed motor is placed, such as in industrial process and automotive applications. Each monitored segment of rotation corresponds to the motor rotational switching sequence of a motor driver circuit, a digital counter generates a running total rotational count and increments or decrements the total count depending upon the direction of motor rotation.

Abstract: A fault detection circuit monitors voltage drops associated with phase windings of a brushed or brushless reversible multi-phase motor and compares them with reference voltages to determine if the motor is out of normal operating range parameters and if a valid fault condition exists. The fault detection circuit-is included in a motor control circuit and is configurable for use with a wide variety of motors having a broad range of load characteristics. The fault detection circuit includes a programmable clock generator which generates time delays for masking faults detected during start-up and during motor phase sequencing. The fault detection circuit thereby avoids transient and spurious faults and prevents the unnecessary termination of motor operation. The length of the mask time delay required for effective fault detection operation depends on the load characteristics of the selected motor.