Patents by Inventor Abhijit Abhyankar

Abhijit Abhyankar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070088968
    Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.
    Type: Application
    Filed: November 15, 2006
    Publication date: April 19, 2007
    Applicant: RAMBUS, INC.
    Inventors: Scott Best, Abhijit Abhyankar, Kun Chang, Frank Lambrecht
  • Patent number: 7057460
    Abstract: A differential amplifier with adaptive biasing and offset cancellation is disclosed. In one particular exemplary embodiment, the differential amplifier may comprise a first electrical path comprising a first transistor and a first resistance element, and a second electrical path comprising a second transistor and a second resistance element, where the first and the second electrical paths are coupled to a voltage source on one end and to a current source on the other end. The differential amplifier may further comprise a first adjustable current source coupled between the voltage source and a first node located between the first transistor and the first resistance element, and a second adjustable current source coupled between the voltage source and a second node located between the second transistor and the second resistance element, wherein the first and second adjustable current sources provide biasing currents for the two electrical paths.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: June 6, 2006
    Assignee: Rambus, Inc.
    Inventors: Kambiz Kaviani, Kun-Yung Chang, Abhijit Abhyankar
  • Publication number: 20060031698
    Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.
    Type: Application
    Filed: October 4, 2005
    Publication date: February 9, 2006
    Applicant: RAMBUS, INC.
    Inventors: Scott Best, Abhijit Abhyankar, Kun-Yung Chang, Frank Lambrecht
  • Publication number: 20060022724
    Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.
    Type: Application
    Filed: September 27, 2005
    Publication date: February 2, 2006
    Inventors: Jared Zerbe, Michael Ching, Abhijit Abhyankar, Richard Barth, Andy Chan, Paul Davis, William Stonecypher
  • Publication number: 20050285678
    Abstract: A differential amplifier with adaptive biasing and offset cancellation is disclosed. In one particular exemplary embodiment, the differential amplifier may comprise a first electrical path comprising a first transistor and a first resistance element, and a second electrical path comprising a second transistor and a second resistance element, where the first and the second electrical paths are coupled to a voltage source on one end and to a current source on the other end. The differential amplifier may further comprise a first adjustable current source coupled between the voltage source and a first node located between the first transistor and the first resistance element, and a second adjustable current source coupled between the voltage source and a second node located between the second transistor and the second resistance element, wherein the first and second adjustable current sources provide biasing currents for the two electrical paths.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 29, 2005
    Inventors: Kambiz Kaviani, Kun-Yung Chang, Abhijit Abhyankar
  • Publication number: 20050210308
    Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.
    Type: Application
    Filed: March 17, 2004
    Publication date: September 22, 2005
    Applicant: RAMBUS, INC.
    Inventors: Scott Best, Abhijit Abhyankar, Kun-Yung Chang, Frank Lambrecht
  • Publication number: 20050160241
    Abstract: A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.
    Type: Application
    Filed: February 15, 2005
    Publication date: July 21, 2005
    Inventors: Richard Barth, Frederick Ware, Donald Stark, Craig Hampel, Paul Davis, Abhijit Abhyankar, James Gasbarro, David Nguyen