Patents by Inventor Abhijit Anant Patki
Abhijit Anant Patki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11265191Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.Type: GrantFiled: July 31, 2020Date of Patent: March 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Nikolaus Klemmer, Amneh Mohammed Akour, Abhijit Anant Patki, Timothy Patrick Pauletti, Tarkesh Pande
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Patent number: 11196596Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.Type: GrantFiled: September 11, 2020Date of Patent: December 7, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Nikolaus Klemmer, Amneh Mohammed Akour, Abhijit Anant Patki, Timothy Patrick Pauletti, Tarkesh Pande
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Patent number: 11082271Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.Type: GrantFiled: June 12, 2020Date of Patent: August 3, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Subhashish Mukherjee, Abhijit Anant Patki, Madhulatha Bonu, Kumar Anurag Shrivastava
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Publication number: 20200412588Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.Type: ApplicationFiled: September 11, 2020Publication date: December 31, 2020Inventors: Nikolaus Klemmer, Amneh Mohammed Akour, Abhijit Anant Patki, Timothy Patrick Pauletti, Tarkesh Pande
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Publication number: 20200366540Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.Type: ApplicationFiled: July 31, 2020Publication date: November 19, 2020Inventors: Nikolaus Klemmer, Amneh Mohammed Akour, Abhijit Anant Patki, Timothy Patrick Pauletti, Tarkesh Pande
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Patent number: 10797921Abstract: A threshold computation circuit includes an input circuit, a maximum filter circuit, a minimum filter circuit, and a calculating circuit. The input circuit receives a discrete frequency signal from a digital filtering circuit. The discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filtering circuit. The discrete frequency signal is representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. The maximum filter circuit adjusts a maximum amplitude parameter based on the discrete frequency signal and a predetermined threshold. The minimum filter circuit adjusts a minimum amplitude parameter based on the discrete frequency signal and the predetermined threshold. The calculating circuit adapts the predetermined threshold for a next data frame based on the maximum and minimum amplitude parameters. An integrated circuit and a method for computing the threshold are also disclosed.Type: GrantFiled: June 24, 2019Date of Patent: October 6, 2020Assignee: Texas Instruments IncorporatedInventors: Nikolaus Klemmer, Amneh Mohammed Akour, Abhijit Anant Patki, Timothy Patrick Pauletti
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Publication number: 20200313945Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.Type: ApplicationFiled: June 12, 2020Publication date: October 1, 2020Inventors: Subhashish Mukherjee, Abhijit Anant Patki, Madhulatha Bonu, Kumar Anurag Shrivastava
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Publication number: 20200304139Abstract: A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.Type: ApplicationFiled: October 23, 2019Publication date: September 24, 2020Inventors: Uttam Kumar AGARWAL, Anand KANNAN, Ramamurthy VISHWESHWARA, Anand SUBRAMANIAN, Pedro Ramon GELABERT, Diljith Mathal THODI, Abhijit Anant PATKI
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Patent number: 10778482Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.Type: GrantFiled: July 18, 2019Date of Patent: September 15, 2020Assignee: Texas Instruments IncorporatedInventors: Nikolaus Klemmer, Amneh Mohammed Akour, Abhijit Anant Patki, Timothy Patrick Pauletti, Tarkesh Pande
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Patent number: 10763889Abstract: A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.Type: GrantFiled: October 23, 2019Date of Patent: September 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Uttam Kumar Agarwal, Anand Kannan, Ramamurthy Vishweshwara, Anand Subramanian, Pedro Ramon Gelabert, Diljith Mathal Thodi, Abhijit Anant Patki
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Publication number: 20200259687Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.Type: ApplicationFiled: July 18, 2019Publication date: August 13, 2020Inventors: Nikolaus Klemmer, Amneh Mohammed Akour, Abhijit Anant Patki, Timothy Patrick Pauletti, Tarkesh Pande
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Publication number: 20200259690Abstract: A threshold computation circuit includes an input circuit, a maximum filter circuit, a minimum filter circuit, and a calculating circuit. The input circuit receives a discrete frequency signal from a digital filtering circuit. The discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filtering circuit. The discrete frequency signal is representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. The maximum filter circuit adjusts a maximum amplitude parameter based on the discrete frequency signal and a predetermined threshold. The minimum filter circuit adjusts a minimum amplitude parameter based on the discrete frequency signal and the predetermined threshold. The calculating circuit adapts the predetermined threshold for a next data frame based on the maximum and minimum amplitude parameters. An integrated circuit and a method for computing the threshold are also disclosed.Type: ApplicationFiled: June 24, 2019Publication date: August 13, 2020Inventors: Nikolaus Klemmer, Amneh Mohammed Akour, Abhijit Anant Patki, Timothy Patrick Pauletti
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Patent number: 10728068Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.Type: GrantFiled: January 3, 2018Date of Patent: July 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Subhashish Mukherjee, Abhijit Anant Patki, Madhulatha Bonu, Kumar Anurag Shrivastava
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Publication number: 20180131545Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.Type: ApplicationFiled: January 3, 2018Publication date: May 10, 2018Inventors: Subhashish Mukherjee, Abhijit Anant Patki, Madhulatha Bonu, Kumar Anurag Shrivastava
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Patent number: 9893916Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop.Type: GrantFiled: July 1, 2016Date of Patent: February 13, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Subhashish Mukherjee, Abhijit Anant Patki, Madhulatha Bonu, Kumar Anurag Shrivastava
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Publication number: 20180006856Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop.Type: ApplicationFiled: July 1, 2016Publication date: January 4, 2018Inventors: Subhashish Mukherjee, Abhijit Anant Patki, Madhulatha Bonu, Kumar Anurag Shrivastava