Abstract: A method of improving performance of a dual Vt integrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint.

Abstract: A slack time, based on a required and actual delay time, is calculated for each node in a circuit (302). For each element in the circuit, a sensitivity (304) and a figure of merit (306) is calculated. A variance is determined for the calculated figure of merits (308). The circuit element having the smallest absolute figure or merit is optimized when the variance is smaller than a predefined threshold (310, 312).

Abstract: A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409).

Abstract: A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409).

Abstract: A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407,409).