Patents by Inventor Abhijit M. Abhyankar
Abhijit M. Abhyankar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11907555Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.Type: GrantFiled: November 18, 2022Date of Patent: February 20, 2024Assignee: Rambus Inc.Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
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Patent number: 11669124Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.Type: GrantFiled: April 7, 2022Date of Patent: June 6, 2023Assignee: Rambus Inc.Inventors: Scott C. Best, Abhijit M. Abhyankar, Kun-Yung Chang, Frank Lambrecht
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Publication number: 20230138512Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.Type: ApplicationFiled: November 18, 2022Publication date: May 4, 2023Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
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Patent number: 11520508Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.Type: GrantFiled: May 21, 2020Date of Patent: December 6, 2022Assignee: Rambus Inc.Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
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Publication number: 20220300030Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.Type: ApplicationFiled: April 7, 2022Publication date: September 22, 2022Inventors: Scott C. Best, Abhijit M. Abhyankar, Kun-Yung Chang, Frank Lambrecht
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Patent number: 11327524Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.Type: GrantFiled: December 9, 2019Date of Patent: May 10, 2022Assignee: Rambus Inc.Inventors: Scott C. Best, Abhijit M. Abhyankar, Kun-Yung Chang, Frank Lambrecht
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Publication number: 20200348870Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.Type: ApplicationFiled: May 21, 2020Publication date: November 5, 2020Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
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Publication number: 20200209911Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.Type: ApplicationFiled: December 9, 2019Publication date: July 2, 2020Inventors: Scott C. Best, Abhijit M. Abhyankar, Kun-Yung Chang, Frank Lambrecht
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Patent number: 10686448Abstract: An integrated circuit comprising (1) an array of logic tiles including a first and a second plurality of logic tiles, wherein each logic tile of the array is configurable to electrically connect with at least one other logic tile, and (2) a clock mesh fabric to provide a mesh clock signal to the first plurality of the logic tiles. Each logic tile of the first plurality includes clock distribution and transmission circuitry including: (1) tile clock generation circuitry configurable to generate a tile clock signal having a skew which is balanced with respect to the tile clock signals of each logic tile of the first plurality of logic tiles, and (2) clock selection circuitry configurable to receive the mesh clock signal and the tile clock signal and responsively output the tile clock to the circuitry which performs operations using or based on the associated tile clock.Type: GrantFiled: July 8, 2019Date of Patent: June 16, 2020Assignee: Flex Logix Technologies, Inc.Inventors: Nitish U. Natu, Abhijit M. Abhyankar, Cheng C. Wang
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Patent number: 10678459Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.Type: GrantFiled: July 14, 2016Date of Patent: June 9, 2020Assignee: Rambus Inc.Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
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Patent number: 10503201Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.Type: GrantFiled: June 7, 2017Date of Patent: December 10, 2019Assignee: Rambus Inc.Inventors: Scott C. Best, Abhijit M. Abhyankar, Kun-Yung Chang, Frank Lambrecht
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Publication number: 20190334527Abstract: An integrated circuit comprising (1) an array of logic tiles including a first and a second plurality of logic tiles, wherein each logic tile of the array is configurable to electrically connect with at least one other logic tile, and (2) a clock mesh fabric to provide a mesh clock signal to the first plurality of the logic tiles. Each logic tile of the first plurality includes clock distribution and transmission circuitry including: (1) tile clock generation circuitry configurable to generate a tile clock signal having a skew which is balanced with respect to the tile clock signals of each logic tile of the first plurality of logic tiles, and (2) clock selection circuitry configurable to receive the mesh clock signal and the tile clock signal and responsively output the tile clock to the circuitry which performs operations using or based on the associated tile clock.Type: ApplicationFiled: July 8, 2019Publication date: October 31, 2019Applicant: Flex Logix Technologies, Inc.Inventors: Nitish U. Natu, Abhijit M. Abhyankar, Cheng C. Wang
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Patent number: 10411711Abstract: An integrated circuit comprising a physical array of logic tiles, wherein each logic tile includes a perimeter and a plurality of external I/O disposed in a layout on the perimeter of the logic tile wherein the layout of the external I/O of each logic tile is identical. The physical array includes a first virtual array of logic tiles, programmed to perform data processing operations, including a first plurality of logic tiles of the physical array. The physical array also includes a second virtual array of logic tiles, programmed to perform second operations, including a second plurality of logic tiles of the physical array. The logic tiles of the second plurality are different from the logic tiles of the first plurality. In one embodiment, performance of the data processing operations of the first virtual array is independent from performance of the second operations of the second virtual array.Type: GrantFiled: May 9, 2018Date of Patent: September 10, 2019Assignee: Flex Logix Technologies, Inc.Inventors: Anthony Kozaczuk, Cheng C. Wang, Abhijit M. Abhyankar
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Patent number: 10348308Abstract: An integrated circuit comprising (i) an array of logic tiles wherein each logic tile is configurable to connect with at least one adjacent logic tile and (ii) a clock mesh fabric including a clock mesh to provide a mesh clock signal to each of the logic tiles of the array of logic tiles. In one embodiment, each logic tile of the array of logic tiles includes (1) distribution and transmission circuitry configurable to provide an associated tile clock to circuitry which performs operations using or based on the associated tile clock, wherein the distribution and transmission circuitry includes circuitry to generate a tile clock signal having a skew which is balanced with respect to the tile clock signals generated by the generation circuitry of each tile, and (2) selection circuitry to responsively output the associated tile clock which corresponds to the mesh clock signal or the tile clock signal.Type: GrantFiled: June 15, 2018Date of Patent: July 9, 2019Assignee: Flex Logix Technologies, Inc.Inventors: Nitish U. Natu, Abhijit M. Abhyankar, Cheng C. Wang
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Publication number: 20190007047Abstract: An integrated circuit comprising (i) an array of logic tiles wherein each logic tile is configurable to connect with at least one adjacent logic tile and (ii) a clock mesh fabric including a clock mesh to provide a mesh clock signal to each of the logic tiles of the array of logic tiles. In one embodiment, each logic tile of the array of logic tiles includes (1) distribution and transmission circuitry configurable to provide an associated tile clock to circuitry which performs operations using or based on the associated tile clock, wherein the distribution and transmission circuitry includes circuitry to generate a tile clock signal having a skew which is balanced with respect to the tile clock signals generated by the generation circuitry of each tile, and (2) selection circuitry to responsively output the associated tile clock which corresponds to the mesh clock signal or the tile clock signal.Type: ApplicationFiled: June 15, 2018Publication date: January 3, 2019Applicant: Flex Logix Technologies, Inc.Inventors: Nitish U. Natu, Abhijit M. Abhyankar, Cheng C. Wang
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Publication number: 20180343010Abstract: An integrated circuit comprising a physical array of logic tiles, wherein each logic tile includes a perimeter and a plurality of external I/O disposed in a layout on the perimeter of the logic tile wherein the layout of the external I/O of each logic tile is identical. The physical array includes a first virtual array of logic tiles, programmed to perform data processing operations, including a first plurality of logic tiles of the physical array. The physical array also includes a second virtual array of logic tiles, programmed to perform second operations, including a second plurality of logic tiles of the physical array. The logic tiles of the second plurality are different from the logic tiles of the first plurality. In one embodiment, performance of the data processing operations of the first virtual array is independent from performance of the second operations of the second virtual array.Type: ApplicationFiled: May 9, 2018Publication date: November 29, 2018Applicant: Flex Logix Technologies, Inc.Inventors: Anthony Kozaczuk, Cheng C. Wang, Abhijit M. Abhyankar
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Publication number: 20180285013Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.Type: ApplicationFiled: July 14, 2016Publication date: October 4, 2018Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
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Publication number: 20170344050Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.Type: ApplicationFiled: June 7, 2017Publication date: November 30, 2017Inventors: Scott C. Best, Abhijit M. Abhyankar, Kun-Yung Chang, Frank Lambrecht
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Patent number: 9710011Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.Type: GrantFiled: June 26, 2015Date of Patent: July 18, 2017Assignee: Rambus Inc.Inventors: Scott C. Best, Abhijit M. Abhyankar, Kun-Yung Chang, Frank Lambrecht
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Patent number: 9298228Abstract: A computing system having a memory riser sub-system. The computing system includes a motherboard with a memory module connector and a riser card inserted into the first memory module connector. A first mezzanine card is connected to the riser card. The first mezzanine card includes a first mezzanine memory module connector for a first memory module and a second mezzanine memory module connector for a second memory module. A memory channel electrically connects the memory controller to the first mezzanine memory module connector and the second mezzanine module connector via the motherboard, the first riser card and the first mezzanine card. The memory channel may be divided into a first data sub-channel connected to the first mezzanine memory module connector and a second data sub-channel connected to the second mezzanine memory module connector.Type: GrantFiled: July 27, 2015Date of Patent: March 29, 2016Assignee: Rambus Inc.Inventors: Abhijit M. Abhyankar, Ravindranath Kollipara, Thomas J. Giovannini, Ming Li, David A. Secker, Arun Vaidyanath, Donald R. Mullen, Adrian F. Torres