Patents by Inventor Abhijit M. Phanse

Abhijit M. Phanse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030235145
    Abstract: A crosstalk compensation engine for reducing signal crosstalk effects within a data signal. Demultiplexed data signals corresponding to multiplexed data signals received via a signal transmission medium are processed to significantly reduce one or more signal crosstalk products related to one or more interactions among the multiplexed data signals within the signal transmission medium. Such signal crosstalk products include those resulting from dense wavelength-division mutiplexing of the data signals used to provide the multiplexed data signals, four-wave mixing among the multiplexed data signals within the signal transmission medium, and cross-phase modulation among the multiplexed data signals within the signal transmission medium.
    Type: Application
    Filed: June 24, 2002
    Publication date: December 25, 2003
    Inventors: Abhijit G. Shanbhag, Abhijit M. Phanse
  • Patent number: 6642793
    Abstract: There is disclosed a differential current mirror system and method for providing differential output current signals that are proportional to differential input current signals in which common mode current signals are rejected. The system comprises a pair of diode connected transistors and a differential amplifier. The pair of diode connected transistors comprises a first and second transistor coupled together. The differential amplifier comprises a third and fourth transistor coupled together in a differential amplifier configuration. The gate of the third transistor receives a first input current signal from the drain of the first transistor and the gate of the fourth transistor receives a second input current signal from the drain of the second transistor.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: November 4, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Abhijit M. Phanse, Michael X. Maida
  • Publication number: 20030189997
    Abstract: In accordance with the presently claimed invention, compensation for reducing ISI products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium introduces distinct compensation effects for individual ISI products within the electrical data signal. Distinct data signal components within the detected data signal and corresponding to such ISI products can be selectively and individually compensated, thereby producing a compensated data signal in which each selected one of such individual data signal components is substantially removed. Individual data signal components or selected combinations of data signal components can be compensated as desired.
    Type: Application
    Filed: September 16, 2002
    Publication date: October 9, 2003
    Inventors: Abhijit G. Shanbhag, Abhijit M. Phanse
  • Publication number: 20030189996
    Abstract: A compensation circuit for reducing intersymbol interference (ISI) products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium provides for selective application of compensation to individual, discrete data signal components. According to one embodiment, one circuit branch processes the electrical data signal to substantially remove one distinct signal component representing an ISI product of some portion of the data symbol sequence. A second circuit branch approximately duplicates an ISI product of another portion of the data symbol sequence for removal by subtraction within a signal combiner from the compensated signal provided by the first circuit branch. A third circuit branch approximately duplicates an ISI product of still another portion of the data symbol sequence also for removal by subtraction within the signal combiner from the compensated signal provided by the first circuit branch.
    Type: Application
    Filed: April 5, 2002
    Publication date: October 9, 2003
    Inventors: Abhijit G. Shanbhag, Abhijit M. Phanse
  • Patent number: 6590454
    Abstract: There is disclosed a system and method for current splitting for variable gain control. The system comprises a current splitting circuit that splits an input current into a first current portion that is proportional to a first scale factor that has a value between zero and one. The remainder of the current is a second current portion that is proportional to a second scale factor that has a value that is equal to one minus the first scale factor. The current splitting circuit comprises a differential current mirror circuit that rejects common mode input current signals.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: July 8, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Abhijit M. Phanse, Michael X. Maida
  • Patent number: 6486735
    Abstract: There is disclosed an adaptive equalizer filter with a current splitting system for variable gain control. The system comprises a current splitting circuit that splits an input current into a first current portion that is proportional to a first scale factor that has a value between zero and one. The remainder of the current is a second current portion that is proportional to a second scale factor that has a value that is equal to one minus the first scale factor. The current splitting circuit comprises a differential current mirror circuit that rejects common mode input current signals.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: November 26, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Abhijit M. Phanse, Michael X. Maida
  • Publication number: 20020135421
    Abstract: There is disclosed a differential current mirror system and method for providing differential output current signals that are proportional to differential input current signals in which common mode current signals are rejected. The system comprises a pair of diode connected transistors and a differential amplifier. The pair of diode connected transistors comprises a first and second transistor coupled together. The differential amplifier comprises a third and fourth transistor coupled together in a differential amplifier configuration. The gate of the third transistor receives a first input current signal from the drain of the first transistor and the gate of the fourth transistor receives a second input current signal from the drain of the second transistor.
    Type: Application
    Filed: April 11, 2002
    Publication date: September 26, 2002
    Applicant: National Semiconductor Corporation
    Inventors: Abhijit M. Phanse, Michael X. Maida
  • Publication number: 20020125951
    Abstract: There is disclosed a system and method for current splitting for variable gain control. The system comprises a current splitting circuit that splits an input current into a first current portion that is proportional to a first scale factor that has a value between zero and one. The remainder of the current is a second current portion that is proportional to a second scale factor that has a value that is equal to one minus the first scale factor. The current splitting circuit comprises a differential current mirror circuit that rejects common mode input current signals.
    Type: Application
    Filed: March 18, 2002
    Publication date: September 12, 2002
    Applicant: National Semiconductor Corporation
    Inventors: Abhijit M. Phanse, Michael X. Maida
  • Patent number: 6407637
    Abstract: There is disclosed a differential current mirror system and method for providing differential output current signals that are proportional to differential input current signals in which common mode current signals are rejected. The system comprises a pair of diode connected transistors and a differential amplifier. The pair of diode connected transistors comprises a first and second transistor coupled together. The differential amplifier comprises a third and fourth transistor coupled together in a differential amplifier configuration. The gate of the third transistor receives a first input current signal from the drain of the first transistor and the gate of the fourth transistor receives a second input current signal from the drain of the second transistor.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: June 18, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Abhijit M. Phanse, Michael X. Maida
  • Patent number: 6373338
    Abstract: There is disclosed a differential current mirror system and method for providing differential output current signals that are proportional to differential input current signals in which common mode current signals are rejected. The system comprises a pair of diode connected transistors and a differential amplifier. The pair of diode connected transistors comprises a first and second transistor coupled together. The differential amplifier comprises a third and fourth transistor coupled together in a differential amplifier configuration. The gate of the third transistor receives a first input current signal from the drain of the first transistor and the gate of the fourth transistor receives a second input current signal from the drain of the second transistor.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: April 16, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Abhijit M. Phanse, Michael X. Maida
  • Patent number: 6359511
    Abstract: There is disclosed a system and method for current splitting for variable gain control. The system comprises a current splitting circuit that splits an input current into a first current portion that is proportional to a first scale factor that has a value between zero and one. The remainder of the current is a second current portion that is proportional to a second scale factor that has a value that is equal to one minus the first scale factor. The current splitting circuit comprises a differential current mirror circuit that rejects common mode input current signals.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: March 19, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Abhijit M. Phanse, Michael X. Maida