Patents by Inventor Abhijit Mukund Abhyankar

Abhijit Mukund Abhyankar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory system with channel multiplexing of multiple memory devices
    Patent number: 7039782
    Abstract: A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: May 2, 2006
    Assignee: Rambus Inc.
    Inventors: Billy Wayne Garrett, Jr., Frederick Abbott Ware, Craig E. Hampel, Richard M. Barth, Donald C. Stark, Abhijit Mukund Abhyankar, Catherine Yuhjung Chen, Thomas J. Sheffler, Ely K. Tsern, Steven Cameron Woo
  • Memory module with offset data lines and bit line swizzle configuration
    Patent number: 6839266
    Abstract: A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: January 4, 2005
    Assignee: Rambus Inc.
    Inventors: Billy Wayne Garrett, Jr., Frederick Abbott Ware, Craig E. Hampel, Richard M. Barth, Don Stark, Abhijit Mukund Abhyankar, Catherine Yuhjung Chen, Thomas J. Sheffler, Ely K. Tsern, Steven Cameron Woo
  • Memory system with channel multiplexing of multiple memory devices
    Publication number: 20040081005
    Abstract: A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.
    Type: Application
    Filed: October 20, 2003
    Publication date: April 29, 2004
    Applicant: Rambus Inc.
    Inventors: Billy Wayne Garrett, Frederick Abbott Ware, Craig E. Hampel, Richard M. Barth, Donald C. Stark, Abhijit Mukund Abhyankar, Catherine Yuhjung Chen, Thomas J. Sheffler, Ely K. Tsern, Steven Cameron Woo
  • Memory system with channel multiplexing of multiple memory devices
    Patent number: 6708248
    Abstract: A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: March 16, 2004
    Assignee: Rambus Inc.
    Inventors: Billy Wayne Garrett, Jr., Frederick Abbott Ware, Craig E. Hampel, Richard M. Barth, Donald C. Stark, Abhijit Mukund Abhyankar, Catherine Yuhjung Chen, Thomas J. Sheffler, Ely K. Tsern, Steven Cameron Woo
  • High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes
    Patent number: 6370668
    Abstract: The present invention provides a high data bandwidth memory system capable of operating in non-chip-kill and chip-kill modes. In chip-kill mode, cycle multiplexing, bit multiplexing, and time and space multiplexing are used to read/write data and syndrome across a group of memory devices. Current command packet formats are adapted to communicate with the group of memory devices in chip-kill mode.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: April 9, 2002
    Assignee: Rambus INC
    Inventors: Billy Wayne Garrett, Jr., Frederick Abbott Ware, Craig E. Hampel, Richard M. Barth, Don Stark, Abhijit Mukund Abhyankar, Catherine Yuhjung Chen, Thomas J. Sheffler, Ely K. Tsern, Steven Cameron Woo