Abstract: An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.

Abstract: An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, thereby producing more adaptive filter tap coefficient signals for significantly improved and robust signal equalization.

Abstract: An adaptive coefficient signal generator for use in an adaptive signal equalizer with fractionally-spaced feedback. The signals representing the feedback tap coefficients are generated in conjunction with a timing interpolation parameter such that the fractionally-spaced feedback circuitry dynamically emulates symbol-spaced feedback circuitry.

Abstract: An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, thereby producing more adaptive filter tap coefficient signals for significantly improved and robust signal equalization.

Abstract: An adaptive coefficient signal generator for use in an adaptive signal equalizer with fractionally-spaced feedback. The signals representing the feedback tap coefficients are generated in conjunction with a timing interpolation parameter such that the fractionally-spaced feedback circuitry dynamically emulates symbol-spaced feedback circuitry.

Abstract: A compensation circuit and method for reducing ISI products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium introduces distinct compensation effects for individual ISI products within the electrical data signal. Distinct data signal components within the detected data signal and corresponding to such ISI products can be selectively and individually compensated, thereby producing a compensated data signal in which each selected one of such individual data signal components is substantially removed. Individual data signal components or selected combinations of data signal components can be compensated as desired.

Abstract: A closed feedback loop controls the slicing, or detecting, of an incoming data signal. Detected signal information about the positive and negative peaks of the incoming data signal is processed to generate positive and negative peak reference signals which serve as reference signal levels for establishing the thresholds at which signal slicing takes place.

Abstract: A signal gating controller for recovering true data signal pulses while gating out false data signal pulses which are generated and prevent convergence when recovering a multilevel data signal, such as an MLT3 Ethernet signal, which has been severely over-equalized. A signal slicing circuit generates two data peak signals: one data peak signal identifies occurrences of positive data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding zero and positive peak signal levels; the other data peak signal identifies occurrences of negative data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding zero and negative peak signal levels. A signal gating control circuit sequentially latches such data peak signals to produce two gating control signals.

Abstract: A gain controller for a signal mixer in which consistent circuit gain is maintained by using transistors in the gain control and signal mixing stages with equal corresponding device dimensions and by using a differential gain control voltage with inverse and noninverse differential voltage phases which individually track variations in the dc bias currents used to power the gain control and signal mixing stages. This provides a gain factor which is independent of variations in circuit operation due to variations in circuit manufacturing processes and operating voltages and temperatures. Such a gain controller provides a self-compensating gain control signal which is based upon a variable gain control factor and tracks variations in circuit operation due to variations in circuit manufacturing processes and operating voltages and temperatures by tracking variations in the dc biasing used to power the gain control and signal mixing stages.

Abstract: A data signal peak error detector for monitoring and detecting undesired shifts in the peak levels of a multilevel data signal, such as an MLT3 Ethernet signal. A signal slicing circuit generates two signals: a data peak detection signal identifies occurrences of data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding intermediate and peak (e.g., positive or negative) signal levels; and a data peak error signal identifies occurrences of data signal peak errors and is asserted when the input data signal level has transitioned beyond a value which corresponds to a preceding peak signal level. Assertion of the data peak detection signal initiates a count sequence by a counter. The count sequence is decoded to produce one or more signal pulses, each of which is provided at a respective time after assertion of the first data peak signal and identifies a valid state of the data peak error signal.

Abstract: A closed feedback loop controls the baseline correction of a data signal. Detected signal information about the baseline and positive and negative peaks of the incoming data signal is processed to generate a baseline correction signal which identifies the difference, if any, between the present data signal baseline and that which is desired. This baseline correction signal is summed with the original data signal to bring its baseline into conformance with the desired baseline.

Abstract: A closed feedback loop controls the adaptive equalization of an incoming data signal received via a cable. Detected signal information about the positive and negative peaks of the incoming data signal during different windows in time is processed to generate a set of adaptive equalization control signals which identify differences, if any, between the positive and negative peaks of the present data signal and those which are desired. These equalization control signals control an input signal equalization circuit which adaptively adjusts the waveshape of the present data signal to bring it into conformance with the desired waveshape.

Abstract: A mixing circuit for combining biasing and signals using a selectively variable signal gain which is independent of the biasing and using biasing which is independent of the selectively variable signal gain. A Gilbert cell is used to multiply a differential control voltage, which represents a normalized signal gain factor, with input currents which include biasing components and input signal components. The resultant output current includes a bias component which is independent of the differential control voltage and a signal component which is independent of the input current biasing components. The gain factor has a value between zero and unity which varies in relation to the differential input control voltage.

Abstract: A distributive encoder for receiving and processing digital error signals representing variations in peak values of an equalized incoming digital data signal and in accordance therewith encoding error signals which represent signal peak errors in data signals for purposes of identifying erroneous signal baseline, peak and equalization conditions. The digital error signals represent variations in peak values of an equalized incoming digital data signal which includes a data signal baseline intermediate to its positive and negative peaks. Two sets of the digital error signals identify when present positive and negative levels transcend prior positive and negative levels, respectively, of the equalized incoming digital data signal. Using various subsets of these digital error signals, the distributive encoder generates encoded error signals which identify erroneous signal baseline, peak and equalization conditions.

Abstract: A high speed data receiver for recovering binary or MLT3 encoded data which has been received via a cable. An adaptive equalizer provides signal gain which increases with frequency and adapts according to the length of the cable. Control over such adaptive equalizing is achieved by monitoring the peak-to-peak amplitude, amplitude peaks and differences between amplitude peaks of the equalized data signal during defined time intervals. Baseline restoration and dynamic data slicing are also provided.

Abstract: An adaptive equalizer for adaptively equalizing a data signal received via a communications path having a signal loss magnitude which increases with signal frequency includes multiple, serially coupled adaptive filter stages. The input data signal is successively filtered and magnitude weighted by successive adaptive filter circuits in accordance with corresponding, respective adaptation control signals. The frequency domain ratio of output signals to corresponding input signals for each adaptive filter circuit represents a corresponding, respective adaptive filter transfer function. An equalizer controller, in accordance with a single equalization control signal, generates the multiple, individual adaptation control signals.

Abstract: A digital-to-analog converter for converting a multiple bit digital input signal into multiple representative analog output signals includes a pulse density modulator, a logic controller, signal selection logic circuits and resistive-capacitive lowpass output filters. The pulse density modulator receives the N-M least significant bits of an N-bit digital input signal and in accordance therewith generates a pulse density modulated digital signal with a pulse density corresponding to a digital count of such N-M least significant bits. The logic controller receives the M most significant bits of the N-bit digital input signal and in accordance therewith generates multiple pairs of digital control signals. Each of the signal selection logic circuits receives the pulse density modulated digital signal and a respective pair of the digital control signals and in accordance therewith provides a respective one of a number of digital output signals.