Patents by Inventor Abhijit Ray

Abhijit Ray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6175520
    Abstract: A flash EPROM device (100) is disclosed. During a programming operation, a primary programming voltage circuit (116) drives I/O lines (110) to a programming voltage (Vp) according to input data values. Secondary programming voltage circuits (118) are located remotely from the primary programming voltage circuit (116) and further drive I/O lines to Vp in response to the voltage levels on the I/O lines. This arrangement reduces the effect on the load line response of the impedance intermediate the primary programming voltage circuit (116) and the secondary programming voltage circuits (118).
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: January 16, 2001
    Assignee: Alliance Semiconductor Corporation
    Inventors: T. Damodar Reddy, Abhijit Ray
  • Patent number: 6097179
    Abstract: A voltage regulator circuit (100), coupled between a high power supply voltage (VCC) and a lower power supply voltage (VSS), provides a regulated voltage (XDD) that is greater than the high power supply voltage (VCC). The voltage regulator circuit (100) includes a temperature compensating detect circuit (102) which activates a trigger signal when the XDD voltage exceeds a predetermined level. In response to an active trigger signal, a shunt circuit (104) couples the regulated voltage (XDD) to the high power supply voltage (VCC). The regulated voltage (XDD) is translated to the detect circuit (102) by the regulated voltage (XDD) being applied to the gate of a transistor (N112) disposed between the high power supply voltage (VCC) and a detect node (108). This arrangement allows monitoring of the regulated voltage (XDD) level without loading the regulated voltage (XDD).
    Type: Grant
    Filed: March 8, 1999
    Date of Patent: August 1, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijit Ray, Raghava Madhu
  • Patent number: 6016270
    Abstract: A flash memory architecture relies on a single, time-shared address bus to enable a read operation to be performed simultaneously with an algorithm operation when the read operation is targeted for a memory cell block that is not currently tagged for an algorithm operation. After a read address has been latched into the array block selected for the read operation, the address bus is "free" for the remainder of the read operation cycle. During this free time, the address bus can be used for algorithm operations to load the counter address into an active tagged block in the array. Separate global data I/O lines are provided to facilitate simultaneous read and algorithm operations.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: January 18, 2000
    Assignee: Alliance Semiconductor Corporation
    Inventors: Damodar Reddy Thummalapally, Abhijit Ray