Abstract: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.

Abstract: A comparator component having a comparison circuit and bias generator circuit, with the bias generator circuit also having a same number of transistors connected in an identical configuration, as those contained in the comparison circuit to generate a comparison result based on the bias signal generated by the bias generator circuit. A transistor of the comparison circuit receiving the bias signal is connected to a corresponding transistor in the bias generator circuit, in a current mirror configuration. The same bias circuit may be shared by many comparison circuits of corresponding comparator components. The features can be extended to provide hysteresis.

Abstract: A comparator component having a comparison circuit and bias generator circuit, with the bias generator circuit also having a same number of transistors connected in an identical configuration, as those contained in the comparison circuit to generate a comparison result based on the bias signal generated by the bias generator circuit. A transistor of the comparison circuit receiving the bias signal is connected to a corresponding transistor in the bias generator circuit, in a current mirror configuration. The same bias circuit may be shared by many comparison circuits of corresponding comparator components. The features can be extended to provide hysteresis.

Abstract: A circuit and a method for biasing a compound cascode current mirror (CCCM) that enables high-voltage swing at the output and accurate current mirroring is presented. The CCCM has mirror transistors and cascode transistors which may be of a different technology kind. The drain-source voltage Vds of the mirror transistor on the input leg of the CCCM is held at a voltage Vov that is generated by the biasing circuit; Vov is the overdrive voltage of the input mirror transistor of the CCCM and the value of Vov is maintained by the bias circuit and a feed-back amplifier such that the mirror transistor remains on the edge of its active region, over manufacture deviations and tracks even over operational conditions such as temperature and supply variations. The feed-back amplifier drives the gates of the cascode transistors and uses its feedback node to hold the Vds at Vov.

Abstract: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.

Abstract: A circuit and a method for biasing a compound cascode current mirror (CCCM) that enables high-voltage swing at the output and accurate current mirroring is presented. The CCCM has mirror transistors and cascode transistors which may be of a different technology kind. The drain-source voltage Vds of the mirror transistor on the input leg of the CCCM is held at a voltage Vov that is generated by the biasing circuit; Vov is the overdrive voltage of the input mirror transistor of the CCCM and the value of Vov is maintained by the bias circuit and a feed-back amplifier such that the mirror transistor remains on the edge of its active region, over manufacture deviations and tracks even over operational conditions such as temperature and supply variations. The feed-back amplifier drives the gates of the cascode transistors and uses its feedback node to hold the Vds at Vov.