Patents by Inventor Abhijith Prakash
Abhijith Prakash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972818Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages targeted for each of the memory cells during a program-verify portion of a program operation. The control means is also configured to trim the program verify voltages for each of the data states for a grouping of the memory cells based on quantities of the memory cells having the threshold voltage crossing over between the data states in crossovers in a verify level trimming process.Type: GrantFiled: June 15, 2022Date of Patent: April 30, 2024Assignee: SanDisk Technologies, LLCInventors: Abhijith Prakash, Xiang Yang
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Patent number: 11972808Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings and configured to retain a threshold voltage. The memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes. A control means determines whether a downshift recovery trigger event has occurred in memory operations. In response to determining the downshift recovery trigger event has occurred, the control means inserts at least one of a predetermined idle time in the memory operations and a recovery pulse of a negative voltage to the drain-side select gate transistor of the memory holes of the strings for a predetermined pulse period of time during one of the memory operations.Type: GrantFiled: February 8, 2022Date of Patent: April 30, 2024Assignee: SanDisk Technologies, LLCInventors: Abhijith Prakash, Xiang Yang
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Patent number: 11961573Abstract: A plurality of memory programming the memory cells to at least one programmed data state in a plurality of program-verify iterations. In each iteration, after a programming pulse, a sensing operation is conducted to compare the threshold voltages of the memory cells to a low verify voltage associated with a first programmed data state and to a high very voltage associated with the first programmed data state. The sensing operation includes discharging a sense node through a bit line coupled to one of the memory cells and monitoring a discharge time of the sense node. At least one aspect of the sensing operation is temperature dependent so that a voltage gap between the high and low verify voltages is generally constant across a range of temperatures.Type: GrantFiled: November 23, 2021Date of Patent: April 16, 2024Assignee: SanDisk Technologies, LLCInventors: Abhijith Prakash, Xiang Yang, Dengtao Zhao
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Patent number: 11961572Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including at least one edge word line and other data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage corresponding to data states. The strings are organized in rows and a control means is coupled to the word lines and the strings and identifies the at least one edge word line. The control means programs the memory cells of the strings in particular ones of the rows and associated with the at least one edge word line to have an altered distribution of the threshold voltage for one or more of the data states compared to the memory cells of the strings not in particular ones of the rows and not associated with the at least one edge word line during a program operation.Type: GrantFiled: October 27, 2021Date of Patent: April 16, 2024Assignee: SanDisk Technologies, LLCInventors: Xiang Yang, Abhijith Prakash, Shubhajit Mukherjee
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Publication number: 20240105269Abstract: Systems and methods for bit line modulation to compensate for cell source variation are disclosed. For example, a method for reading data from non-volatile storage comprising determining a first bit line level based on a first programmed data state that is being sensed and determining a second bit line level based on a second programmed data state that is being sensed. As another example, a storage device comprising a first bit line driver configured to generate a first bit line level for a first set of bit lines corresponding to a first set of memory strings based on a first cell source level associated with the first set of memory strings a second bit line driver configured to generate a second bit line level for a second set of bit lines corresponding to a second set of memory strings based on a second cell source level associated with the second set of memory strings.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicant: SanDisk Technologies LLCInventors: Anirudh Amarnath, Aravind Suresh, Abhijith Prakash
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Publication number: 20240105265Abstract: A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.Type: ApplicationFiled: September 26, 2022Publication date: March 28, 2024Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Masaaki Higashitani, Abhijith Prakash, Dengtao Zhao
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Patent number: 11894072Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings. A control means is coupled to the word lines and the strings and is configured to ramp a voltage applied to a selected one of the word lines from a verify voltage to a reduced voltage during a program-verify portion of a program operation. The control means successively ramps voltages applied to each of a plurality of neighboring ones of the word lines from a read pass voltage to the reduced voltage beginning with ones of the plurality of neighboring ones of the word lines immediately adjacent the selected one of the word lines and progressing to ones of the plurality of neighboring others of the word lines disposed increasingly remotely from the selected one of the word lines during the program-verify portion of the program operation.Type: GrantFiled: April 20, 2022Date of Patent: February 6, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Jiacen Guo, Xiang Yang, Abhijith Prakash
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Patent number: 11894051Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a discharge voltage at an end of the read operation and apply a ready voltage to the selected ones of the plurality of word lines during a ready period of time following the read operation. The control means is also configured to adjust at least one of the discharge voltage and the ready voltage based on a temperature of the memory apparatus.Type: GrantFiled: May 24, 2022Date of Patent: February 6, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Dong-Il Moon, Abhijith Prakash, Wei Zhao, Henry Chin
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Patent number: 11894067Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells configured to retain a threshold voltage. The memory cells are connected to one of a plurality of word lines and are arranged in strings comprising a plurality of blocks. A control means is coupled to the plurality of word lines and the strings and is configured to periodically determine a read frequency metric associated with a plurality of read operations of one of the plurality of blocks of the memory cells. The control means is also configured to relocate data of the one of the plurality of blocks and cause the one of the plurality of blocks to remain unused for a predetermined relaxation time based on the read frequency metric.Type: GrantFiled: December 15, 2021Date of Patent: February 6, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Xiang Yang, Abhijith Prakash, Shubhajit Mukherjee
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Publication number: 20230410922Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages targeted for each of the memory cells during a program-verify portion of a program operation. The control means is also configured to trim the program verify voltages for each of the data states for a grouping of the memory cells based on quantities of the memory cells having the threshold voltage crossing over between the data states in crossovers in a verify level trimming process.Type: ApplicationFiled: June 15, 2022Publication date: December 21, 2023Applicant: SanDisk Technologies LLCInventors: Abhijith Prakash, Xiang Yang
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Publication number: 20230410912Abstract: A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory apparatus also includes a control means coupled to the drain-side select gate transistor of each of the plurality of memory holes. The control means is configured to select the transistor threshold voltage of the drain-side select gate transistors as a stable transistor threshold voltage for a grouping of the memory cells to minimize shifting of the transistor threshold voltage following a plurality of read operations of the memory cells. The control means is also configured to program the transistor threshold voltage of the drain-side select gate transistor of the plurality of memory holes associated with the grouping of the memory cells to the stable transistor threshold voltage.Type: ApplicationFiled: June 15, 2022Publication date: December 21, 2023Applicant: SanDisk Technologies LLCInventors: Abhijith Prakash, Xiang Yang
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Publication number: 20230409230Abstract: Memory die management based on biasing voltages. Some memory dies are formed of memory holes having a semi-circular shape. This semi-circular shape results in a decrease in biasing voltage compared to memory holes having a circular shape. Systems and methods described herein organize memory dies into memory die groups according to their biasing voltages. During operation, data is relocated between the memory die groups based on how often the data is read. Data may be scrambled within their respective memory die groups to maintain appropriate storage space.Type: ApplicationFiled: May 17, 2022Publication date: December 21, 2023Inventors: Abhijith Prakash, Xiang Yang
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Publication number: 20230410901Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a discharge voltage at an end of the read operation and apply a ready voltage to the selected ones of the plurality of word lines during a ready period of time following the read operation. The control means is also configured to adjust at least one of the discharge voltage and the ready voltage based on a temperature of the memory apparatus.Type: ApplicationFiled: May 24, 2022Publication date: December 21, 2023Applicant: SanDisk Technologies LLCInventors: Dong-Il Moon, Abhijith Prakash, Wei Zhao, Henry Chin
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Patent number: 11848059Abstract: A method of erasing memory cells in a memory device is provided. The method includes grouping a plurality of word lines into a first group, which does not include edge word lines, and a second group, which does include edge word lines. An erase operation is performed on the memory cells of the first and second groups until erase-verify of the memory cells of the first group passes. It is then determined if further erase of the memory cells of the second group is necessary. In response to it being determined that the additional erase operation is necessary, an additional erase operation is performed on at least some of the memory cells of the second group until erase-verify of the memory cells of the second group passes.Type: GrantFiled: November 18, 2021Date of Patent: December 19, 2023Assignee: SanDisk Technologies LLCInventors: Jiacen Guo, Xiang Yang, Abhijith Prakash
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Publication number: 20230343400Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings. A control means is coupled to the word lines and the strings and is configured to ramp a voltage applied to a selected one of the word lines from a verify voltage to a reduced voltage during a program-verify portion of a program operation. The control means successively ramps voltages applied to each of a plurality of neighboring ones of the word lines from a read pass voltage to the reduced voltage beginning with ones of the plurality of neighboring ones of the word lines immediately adjacent the selected one of the word lines and progressing to ones of the plurality of neighboring others of the word lines disposed increasingly remotely from the selected one of the word lines during the program-verify portion of the program operation.Type: ApplicationFiled: April 20, 2022Publication date: October 26, 2023Applicant: SanDisk Technologies LLCInventors: Jiacen Guo, Xiang Yang, Abhijith Prakash
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Publication number: 20230307070Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings and configured to retain a threshold voltage. The memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes. A control means determines whether a downshift recovery trigger event has occurred in memory operations. In response to determining the downshift recovery trigger event has occurred, the control means inserts at least one of a predetermined idle time in the memory operations and a recovery pulse of a negative voltage to the drain-side select gate transistor of the memory holes of the strings for a predetermined pulse period of time during one of the memory operations.Type: ApplicationFiled: February 8, 2022Publication date: September 28, 2023Applicant: SanDisk Technologies LLCInventors: Abhijith Prakash, Xiang Yang
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Patent number: 11758718Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.Type: GrantFiled: July 14, 2021Date of Patent: September 12, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Yu-Chung Lien, Abhijith Prakash, Keyur Payak, Jiahui Yuan, Huai-Yuan Tseng, Shinsuke Yada, Kazuki Isozumi
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Publication number: 20230253056Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including a dummy word line and other data word lines. The memory cells are disposed in memory holes and configured to retain a threshold voltage. A control means is coupled to the word lines and the memory holes and is configured to determine whether one of the word lines being programmed in a program operation is a particular one of the word lines adjacent the dummy word line needing a dummy positioning operation. The control means is also configured to program the memory cells connected to the dummy word line to adjust the threshold voltage to a predetermined position threshold voltage in the dummy positioning operation in response to determining the one of the plurality of word lines being programmed in the program operation is the particular one of the word lines.Type: ApplicationFiled: February 4, 2022Publication date: August 10, 2023Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Abhijith Prakash
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Publication number: 20230186993Abstract: The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential.Type: ApplicationFiled: February 14, 2023Publication date: June 15, 2023Applicant: SanDisk Technologies LLCInventors: Abhijith Prakash, Anubhav Khandelwal
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Publication number: 20230186998Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells configured to retain a threshold voltage. The memory cells are connected to one of a plurality of word lines and are arranged in strings comprising a plurality of blocks. A control means is coupled to the plurality of word lines and the strings and is configured to periodically determine a read frequency metric associated with a plurality of read operations of one of the plurality of blocks of the memory cells. The control means is also configured to relocate data of the one of the plurality of blocks and cause the one of the plurality of blocks to remain unused for a predetermined relaxation time based on the read frequency metric.Type: ApplicationFiled: December 15, 2021Publication date: June 15, 2023Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Abhijith Prakash, Shubhajit Mukherjee