Patents by Inventor ABHILASH JAIN

ABHILASH JAIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240095896
    Abstract: A method and system for dimension estimation based on duplication identification is disclosed. In some embodiments, the method includes receiving a set of images of an object. The method includes detecting, from each image in the set of images, a respective image segmentation representing a damage of the object. The method then includes determining a respective dimension for the damage represented by each of the image segmentations. The method further includes determining whether two or more of the image segmentations represent a same damage of the object. Responsive to two or more of the image segmentations representing a same damage of the object, the method includes combining the respective dimensions determined for the damage represented by the two or more image segmentations to obtain a final dimension for the same damage.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Abhilash Nvs, Ankit Sati, Payanshi Jain, Koundinya K. Nvss, Rajat Katiyar, Mohiuddin Khan, Chirag Jain, Sreekanth Menon
  • Patent number: 10540326
    Abstract: A dynamically correcting cache memory is capable of correcting itself by dynamically reflecting any modifications inflicted upon the data/information to be stored therein. Further, the cache memory is refreshed at predetermined time intervals and also based on predetermined criteria, thereby ensuring a high cache hit rate. The dynamically correcting cache memory is bypassed for certain user queries prioritized based on a predetermined criteria. The dynamically correcting cache manages an inventory shared between multiple non-cooperative web-based, computer-implemented platforms. The dynamically correcting cache is directed to reducing caching errors in web based computer implemented platforms. The dynamically correcting cache responds to rapid changes associated with (online) behavior of users accessing web based computer implemented platforms by dynamically configuring TTL (Time-To-Live) values, in order to ensure that the data/information stored in the cache memory remains accurate.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: January 21, 2020
    Assignee: MAKEMYTRIP (INDIA) PRIVATE LIMITED
    Inventors: Akshat Verma, Zafar Ansari, Anirban Basu, Abhilash Jain, Pawan Kumar, Sunil Kumar, Vineet Pandita, Dhawal Patel, Rakesh Ranjan, Shubham Srivastava, Sharat Singh
  • Publication number: 20170052976
    Abstract: A computer implemented system and method for implementing a dynamically correcting cache is disclosed. The dynamically correcting cache is capable of correcting itself by dynamically reflecting any modifications inflicted upon the data/information to be stored in the cache memory. Further, the cache memory is refreshed at predetermined time intervals and also based on predetermined criteria, thereby ensuring a high cache hit rate. The dynamically correcting cache memory is bypassed for certain user queries prioritized based on a predetermined criteria. The dynamically correcting cache manages an inventory shared between multiple non-cooperative web-based, computer-implemented platforms. The dynamically correcting cache is directed to reducing caching errors in web based computer implemented platforms.
    Type: Application
    Filed: January 28, 2016
    Publication date: February 23, 2017
    Inventors: AKSHAT VERMA, ZAFAR ANSARI, ANIRBAN BASU, ABHILASH JAIN, PAWAN KUMAR, SUNIL KUMAR, VINEET PANDITA, DHAWAL PATEL, RAKESH RANJAN, SHUBHAM SRIVASTAVA, SHARAT SINGH