Patents by Inventor Abhilash Kaushal

Abhilash Kaushal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock gating for X-bounding timing exceptions in IC testing
    Patent number: 9835683
    Abstract: An integrated circuit includes a clock gate that is used to prevent timing exception paths from affecting data being captured by scan chain registers during at-speed scan testing. A single clock gate can be used to control multiple timing-exception paths, so the amount of X-bounding circuitry inserted into the IC can be drastically reduced compared to that required by conventional X-bounding methodologies.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: December 5, 2017
    Assignee: NXP USA, INC.
    Inventors: Priya Khandelwal, Himanshu Arora, Abhilash Kaushal
  • CLOCK GATING FOR X-BOUNDING TIMING EXCEPTIONS IN IC TESTING
    Publication number: 20170176535
    Abstract: An integrated circuit includes a clock gate that is used to prevent timing exception paths from affecting data being captured by scan chain registers during at-speed scan testing. A single clock gate can be used to control multiple timing-exception paths, so the amount of X-bounding circuitry inserted into the IC can be drastically reduced compared to that required by conventional X-bounding methodologies.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Inventors: Priya Khandelwal, Himanshu Arora, Abhilash Kaushal