Patents by Inventor Abhimanyu Kolla
Abhimanyu Kolla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8559530Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: GrantFiled: October 26, 2007Date of Patent: October 15, 2013Assignee: Intel CorporationInventors: Jerry G. Jex, Jed D. Griffin, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 8149928Abstract: Some embodiments include a transmitter having a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: GrantFiled: May 18, 2010Date of Patent: April 3, 2012Assignee: Intel CorporationInventors: Jed D. Griffin, Jerry G. Jex, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
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Publication number: 20100226419Abstract: Some embodiments include a transmitter having a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: ApplicationFiled: May 18, 2010Publication date: September 9, 2010Inventors: Jed D. Griffin, Jerry G. Jex, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 7720159Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: GrantFiled: October 26, 2007Date of Patent: May 18, 2010Assignee: Intel CorporationInventors: Jed D. Griffin, Jerry G Jex, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 7672335Abstract: A method is described that involves loading X bits at a time into a shift register and shifting groups of older, loaded X bits up in the shift register with each new group of loaded X bits. Each group of X bits has been received from a serial data stream. The method further involves identifying an alignment key within the shift register and presenting aligned data from the serial data stream by rotating selection of a first group of Y contiguous bits from the shift register and a second group of Y contiguous bits from the shift register after the identifying. Y is greater than X.Type: GrantFiled: December 10, 2003Date of Patent: March 2, 2010Assignee: Intel CorporationInventors: Adarsh Panikkar, Wayne C. Ashby, Abhimanyu Kolla
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Patent number: 7656983Abstract: In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.Type: GrantFiled: September 29, 2006Date of Patent: February 2, 2010Assignee: Intel CorporationInventors: Daniel S. Klowden, S. Reji Kumar, Adarsh Panikkar, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 7500131Abstract: Some embodiments of the invention provide a training sequence that may be used in a deskewing process or a protocol to be implemented in a training sequence deskew. Embodiments may also comprise a training pattern that allows for header or frame alignment.Type: GrantFiled: September 7, 2004Date of Patent: March 3, 2009Assignee: Intel CorporationInventors: Adarsh Panikkar, S. Reji Kumar, Daniel Klowden, Abhimanyu Kolla
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Publication number: 20080123722Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: ApplicationFiled: October 26, 2007Publication date: May 29, 2008Inventors: Jerry G. Jex, Jed D. Griffin, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
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Publication number: 20080101505Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: ApplicationFiled: October 26, 2007Publication date: May 1, 2008Inventors: Jed Griffin, Jerry Jex, Arnaud Forestier, Kersi Vakil, Abhimanyu Kolla
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Publication number: 20080080654Abstract: In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.Type: ApplicationFiled: September 29, 2006Publication date: April 3, 2008Inventors: Daniel S. Klowden, S. Reji Kumar, Adarsh Panikkar, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 7308025Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: GrantFiled: July 23, 2003Date of Patent: December 11, 2007Assignee: Intel CorporationInventors: Jerry G. Jex, Jed D. Griffin, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
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Patent number: 7305023Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.Type: GrantFiled: July 23, 2003Date of Patent: December 4, 2007Assignee: Intel CorporationInventors: Jed D. Griffin, Jerry G Jex, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
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Publication number: 20070239906Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for an input/output agent having multiple secondary ports. In some embodiments, the input/output agent includes a primary port to communicate data with an upstream agent over a serial point-to-point interconnect. The input/output agent may also include M secondary ports to communicate data with a corresponding M downstream agents, wherein downstream data is forwarded from the primary port to at least one of the M secondary ports.Type: ApplicationFiled: March 13, 2006Publication date: October 11, 2007Inventors: Kersi Vakil, Abhimanyu Kolla
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Patent number: 7050507Abstract: A signaling apparatus and system may include a data transmitter capable of sending strobe and one or more data streams having edges displaced by time periods corresponding to coded values. Auto-negotiation to compensate for less expensive interconnections may be accomplished using various embodiments of the invention. The data transmitter may be coupled to a medium and a data receiver. An article, including a machine-accessible medium, may contain data capable of causing a machine to carry out a communication method, including transmitting strobe and data streams having edges displaced by time periods corresponding to coded values. A coded information signal may comprise one or more edges displaced in time from various strobe signal edges, the displacement corresponding to coded values.Type: GrantFiled: April 22, 2002Date of Patent: May 23, 2006Assignee: Intel CorporationInventors: Kersi H. Vakil, Jerry G. Jex, Arnaud J. Forestier, Abhimanyu Kolla
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Patent number: 7043392Abstract: According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs associated with the first clock signal, a second plurality of interpolator legs associated with the second clock signal, and an output node to provide an output clock signal having an output clock phase based on the first clock signal, the second clock signal, and on a number of the first plurality and the second plurality of interpolator legs that are activated. The device may also include an interpolator control to activate only one of the first plurality and the second plurality of interpolator legs.Type: GrantFiled: June 16, 2004Date of Patent: May 9, 2006Assignee: Intel CorporationInventors: Kersi H. Vakil, Adarsh Panikkar, Abhimanyu Kolla, Arnaud Forestier
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Publication number: 20060053328Abstract: Some embodiments of the invention provide a training sequence that may be used in a deskewing process or a protocol to be implemented in a training sequence deskew. Embodiments may also comprise a training pattern that allows for header or frame alignment.Type: ApplicationFiled: September 7, 2004Publication date: March 9, 2006Inventors: Adarsh Panikkar, S. Kumar, Daniel Klowden, Abhimanyu Kolla
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Patent number: 7009431Abstract: According to some embodiments, an interpolated clock signal having a first frequency is received, and the interpolated clock signal is periodically sampled based on a reference clock signal to generate periodically-sampled values, the reference clock signal having substantially the first frequency. A phase of the interpolated clock signal may be set to a phase degree at which the periodically-sampled values resolve to more than one value, and the phase of the interpolated clock signal may be incrementally changed until the periodically-sampled values resolve to one value. A non-linearity of the interpolated clock signal may be determined based on the number of incremental changes.Type: GrantFiled: June 29, 2004Date of Patent: March 7, 2006Assignee: Intel CorporationInventors: Adarsh Panikkar, Kersi H. Vakil, Abhimanyu Kolla, Arnaud Forestier
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Publication number: 20050285652Abstract: According to some embodiments, an interpolated clock signal having a first frequency is received, and the interpolated clock signal is periodically sampled based on a reference clock signal to generate periodically-sampled values, the reference clock signal having substantially the first frequency. A phase of the interpolated clock signal may be set to a phase degree at which the periodically-sampled values resolve to more than one value, and the phase of the interpolated clock signal may be incrementally changed until the periodically-sampled values resolve to one value. A non-linearity of the interpolated clock signal may be determined based on the number of incremental changes.Type: ApplicationFiled: June 29, 2004Publication date: December 29, 2005Inventors: Adarsh Panikkar, Kersi Vakil, Abhimanyu Kolla, Arnaud Forestier
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Publication number: 20050280452Abstract: According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs associated with the first clock signal, a second plurality of interpolator legs associated with the second clock signal, and an output node to provide an output clock signal having an output clock phase based on the first clock signal, the second clock signal, and on a number of the first plurality and the second plurality of interpolator legs that are activated. The device may also include an interpolator control to activate only one of the first plurality and the second plurality of interpolator legs.Type: ApplicationFiled: June 16, 2004Publication date: December 22, 2005Inventors: Kersi Vakil, Adarsh Panikkar, Abhimanyu Kolla, Arnaud Forestier
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Publication number: 20050129070Abstract: A method is described that involves loading X bits at a time into a shift register and shifting groups of older, loaded X bits up in the shift register with each new group of loaded X bits. Each group of X bits has been received from a serial data stream. The method further involves identifying an alignment key within the shift register and presenting aligned data from the serial data stream by rotating selection of a first group of Y contiguous bits from the shift register and a second group of Y contiguous bits from the shift register after the identifying. Y is greater than X.Type: ApplicationFiled: December 10, 2003Publication date: June 16, 2005Inventors: Adarsh Panikkar, Wayne Ashby, Abhimanyu Kolla