Patents by Inventor Abhinandan Venugopal
Abhinandan Venugopal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12360692Abstract: Systems, methods, and data storage devices for dynamic mode selection for hybrid MLC/SLC data storage devices are described. Storage operations at a plurality of storage devices from a host device may be processed, wherein each storage device of the plurality of storage devices comprises a plurality of partitions including multi-level cell blocks and single-level cell blocks and multi-level cell blocks may be selectively written in a single-level write operation. A usage value is determined for each partition of the plurality of partitions at each storage device of the plurality of storage devices. A storage device of the plurality of storage devices may be dynamically selected based on the usage value for single-level cell blocks of the selected storage device having available single level cell blocks. New data may then be stored at the dynamically selected storage device of the plurality of storage devices.Type: GrantFiled: August 10, 2023Date of Patent: July 15, 2025Assignee: Sandisk TechnologiesInventors: Amit Sharma, Abhinandan Venugopal
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Patent number: 12333183Abstract: A data storage device receives a speculative read command from a host identifying logical block addresses. The speculative read command is not required be to executed within a certain amount of time or even at all. The data storage device at least partially executes the speculative read command in response to determining that such execution will not reduce performance of the data storage device. At least partially executing the speculative read command causes data associated with at least some of the logical block addresses to be read from the non-volatile memory and stored in at least one buffer. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: GrantFiled: March 31, 2022Date of Patent: June 17, 2025Assignee: Sandisk Technologies, Inc.Inventors: Abhinandan Venugopal, Amit Sharma, Anindita Chakrabarty
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Patent number: 12249396Abstract: In a non-volatile memory system that initially writes data in a binary format and then folds the stored data into a multi-level format, transfers of host data from the memory controller to the memory dies of the system are performed during both foggy and fine phases of the multi-level programming as data latches are released, allowing the transfer times to be hidden behind the programming. To improve data throughput one sub-set of the memory dies perform their foggy phase programming while another sub-set of the memory dies perform their fine phase programming, resulting in non-overlapping transfer windows for host data transfers for the two sub-sets of memory dies.Type: GrantFiled: July 3, 2023Date of Patent: March 11, 2025Assignee: Sandisk Technologies, Inc.Inventors: Abhinandan Venugopal, Amit Sharma
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Publication number: 20250004533Abstract: Techniques are provided for optimizing the power consumption of a data storage device included in a battery-operated device. The battery-operated device (e.g., portable devices like wearable devices, smartwatches, and mobile phones) can access certain data stored on the data storage device more frequently when the device operates on battery power as compared to when the device does not operate on battery power. Techniques are provided for identifying and classifying data into different classifications, for example, power sensitive data and non-power sensitive data. Then the device can optimize the battery power consumption of the data storage device by storing or relocating data stored at the data storage device based on the classification of the data.Type: ApplicationFiled: August 4, 2023Publication date: January 2, 2025Inventors: Amit Sharma, Dinesh Kumar Agarwal, Abhinandan Venugopal
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Publication number: 20250004657Abstract: Systems, methods, and data storage devices for dynamic mode selection for hybrid MLC/SLC data storage devices are described. Storage operations at a plurality of storage devices from a host device may be processed, wherein each storage device of the plurality of storage devices comprises a plurality of partitions including multi-level cell blocks and single-level cell blocks and multi-level cell blocks may be selectively written in a single-level write operation. A usage value is determined for each partition of the plurality of partitions at each storage device of the plurality of storage devices. A storage device of the plurality of storage devices may be dynamically selected based on the usage value for single-level cell blocks of the selected storage device having available single level cell blocks. New data may then be stored at the dynamically selected storage device of the plurality of storage devices.Type: ApplicationFiled: August 10, 2023Publication date: January 2, 2025Inventors: Amit Sharma, Abhinandan Venugopal
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Patent number: 12067293Abstract: A data storage device and method are provided for host multi-command queue grouping based on write-size alignment in a multi-queue-depth environment. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to provide a host with an indication of a required amount of data needed to program a set of multi-level cell blocks in the memory; receive an assurance from the host that the host will be providing the data storage device with the required amount of data; and based on the assurance received from the host, program the set of multi-level cell blocks as data is received from the host but before the required amount of data is received from the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: GrantFiled: May 17, 2022Date of Patent: August 20, 2024Assignee: Sandisk Technologies, Inc.Inventors: Amit Sharma, Dinesh Kumar Agarwal, Abhinandan Venugopal
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Patent number: 12039202Abstract: A programming order of memory dies of a metablock is typically fixed. However, in some storage architectures, this may cause performance bottlenecks. As such, the programming order of the memory dies may be altered to reduce or eliminate performance bottlenecks.Type: GrantFiled: September 16, 2022Date of Patent: July 16, 2024Assignee: Western Digital Technologies, Inc.Inventors: Amit Sharma, Abhinandan Venugopal
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Publication number: 20240221802Abstract: In a non-volatile memory system that initially writes data in a binary format and then folds the stored data into a multi-level format, transfers of host data from the memory controller to the memory dies of the system are performed during both foggy and fine phases of the multi-level programming as data latches are released, allowing the transfer times to be hidden behind the programming. To improve data throughput one sub-set of the memory dies perform their foggy phase programming while another sub-set of the memory dies perform their fine phase programming, resulting in non-overlapping transfer windows for host data transfers for the two sub-sets of memory dies.Type: ApplicationFiled: July 3, 2023Publication date: July 4, 2024Applicant: Western Digital Technologies, Inc.Inventors: Abhinandan Venugopal, Amit Sharma
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Patent number: 11960766Abstract: A data storage device and method for accidental delete protection are provided. In one embodiment, a data storage device comprises a memory and a controller. The memory comprises a first set of physical blocks and a second set of physical blocks, where the first and second sets of physical blocks are associated with separate logical-to-physical address tables and/or separate block lists. The controller is configured to write data received from a host in the first set of physical blocks and move the data from the first set of physical blocks to the second set of physical blocks in response to the host requesting that a modified version of the data be written in the memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: GrantFiled: December 6, 2021Date of Patent: April 16, 2024Assignee: Western Digital Technologies, Inc.Inventors: Abhinandan Venugopal, Amit Sharma
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Patent number: 11941263Abstract: A data storage device having an FTL configured to award to some pending memory operations a higher priority compared to the priority given to those operations by a default scheduling scheme. Such awards of higher priority may be based on a policy directed, e.g., at maximizing the effective data throughput, balancing the data throughput and the input/output bus throughput, or other performance objective. In response to awards of higher priority, a power-management circuit of the data storage device may dynamically route a constrained power supply such that the storage dies corresponding to the higher-priority operations preferentially receive power allocation in the next time interval(s). The remainder of the power budget (if any) in those time intervals may be allocated in accordance with the default scheduling scheme.Type: GrantFiled: May 2, 2022Date of Patent: March 26, 2024Assignee: Western Digital Technologies, Inc.Inventors: Amit Sharma, Niranjana Bhatta, Abhinandan Venugopal
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Publication number: 20240094951Abstract: A programming order of memory dies of a metablock is typically fixed. However, in some storage architectures, this may cause performance bottlenecks. As such, the programming order of the memory dies may be altered to reduce or eliminate performance bottlenecks.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Inventors: Amit Sharma, Abhinandan Venugopal
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Publication number: 20230409234Abstract: A data storage device and method are provided for host multi-command queue grouping based on write-size alignment in a multi-queue-depth environment. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to provide a host with an indication of a required amount of data needed to program a set of multi-level cell blocks in the memory; receive an assurance from the host that the host will be providing the data storage device with the required amount of data; and based on the assurance received from the host, program the set of multi-level cell blocks as data is received from the host but before the required amount of data is received from the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: ApplicationFiled: May 17, 2022Publication date: December 21, 2023Applicant: Western Digital Technologies, Inc.Inventors: Amit Sharma, Dinesh Kumar Agarwal, Abhinandan Venugopal
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Publication number: 20230350586Abstract: A data storage device having an FTL configured to award to some pending memory operations a higher priority compared to the priority given to those operations by a default scheduling scheme. Such awards of higher priority may be based on a policy directed, e.g., at maximizing the effective data throughput, balancing the data throughput and the input/output bus throughput, or other performance objective. In response to awards of higher priority, a power-management circuit of the data storage device may dynamically route a constrained power supply such that the storage dies corresponding to the higher-priority operations preferentially receive power allocation in the next time interval(s). The remainder of the power budget (if any) in those time intervals may be allocated in accordance with the default scheduling scheme.Type: ApplicationFiled: May 2, 2022Publication date: November 2, 2023Inventors: Amit Sharma, Niranjana Bhatta, Abhinandan Venugopal
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Patent number: 11797387Abstract: Example storage systems, storage devices, and methods provide dynamic redundant array of independent disks (RAID) stripe allocation based on memory device health conditions. A device health condition is assigned to each data chunk of a RAID stripe before the data chunk is sent to the target storage device. The write command indicates the device health condition and the receiving storage device selects the storage location for the data chunk corresponding to the device health condition.Type: GrantFiled: June 23, 2020Date of Patent: October 24, 2023Assignee: Western Digital Technologies, Inc.Inventors: Amit Sharma, Dinesh Kumar Agarwal, Abhinandan Venugopal
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Publication number: 20230315335Abstract: A data storage device receives a speculative read command from a host identifying logical block addresses. The speculative read command is not required be to executed within a certain amount of time or even at all. The data storage device at least partially executes the speculative read command in response to determining that such execution will not reduce performance of the data storage device. At least partially executing the speculative read command causes data associated with at least some of the logical block addresses to be read from the non-volatile memory and stored in at least one buffer. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Western Digital Technologies, Inc.Inventors: Abhinandan Venugopal, Amit Sharma, Anindita Chakrabarty
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Patent number: 11775191Abstract: A data storage device including, in one implementation, a non-volatile memory device including a memory block that includes a plurality of memory dies and a controller that is coupled to the non-volatile memory device and that allocates power to non-memory components based on a determined usage of the memory dies. The controller is configured to monitor a utilization of the plurality of memory dies, determine a utilization state of the plurality of memory dies, and calculate an amount of available power allocated to the plurality of memory dies in response to determining that the plurality of memory dies are in a low utilization state. The controller is also configured to determine whether the amount of available power is above a predetermined threshold, and reallocate the available power to one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold.Type: GrantFiled: June 2, 2022Date of Patent: October 3, 2023Assignee: Western Digital Technologies, Inc.Inventors: Amit Sharma, Abhinandan Venugopal, Dinesh Kumar Agarwal, Akhilesh Yadav
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Publication number: 20230176780Abstract: A data storage device and method for accidental delete protection are provided. In one embodiment, a data storage device comprises a memory and a controller. The memory comprises a first set of physical blocks and a second set of physical blocks, where the first and second sets of physical blocks are associated with separate logical-to-physical address tables and/or separate block lists. The controller is configured to write data received from a host in the first set of physical blocks and move the data from the first set of physical blocks to the second set of physical blocks in response to the host requesting that a modified version of the data be written in the memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: ApplicationFiled: December 6, 2021Publication date: June 8, 2023Applicant: Western Digital Technologies, Inc.Inventors: Abhinandan Venugopal, Amit Sharma
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Patent number: 11586384Abstract: The disclosure provides data storage devices, methods, and apparatuses including, among other things, a NAND feature through which software may define logical die groups. Moreover, these logical die groups are indexed and operated with indexed single commands, which is selective-multi-casting to specific dies. In one implementation, a data storage device includes a NAND memory and a controller. The NAND memory including a plurality of dies. The controller is coupled to the NAND memory and configured to generate an index by assigning each die of the plurality of dies to one logical group of a plurality of logical groups, and create the plurality of logical groups in the NAND memory by sending one or more command sequences to the NAND memory that groups the plurality of dies into the plurality of logical groups based on the index that is generated.Type: GrantFiled: February 16, 2021Date of Patent: February 21, 2023Assignee: Western Digital Technologies, Inc.Inventors: Abhinandan Venugopal, Amit Sharma, Vijay Chinchole
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Patent number: 11573706Abstract: A data storage device and method for efficient image searching are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to store a plurality of images and a plurality of keys in the memory, wherein each key of the plurality of keys is generated from a respective image of the plurality of images; receive, from a host, a key generated from a target image desired by the host; and return, to the host, an image from the stored plurality of images that is associated with a key that matches the key received from the host. Other embodiments are provided.Type: GrantFiled: June 7, 2021Date of Patent: February 7, 2023Assignee: Western Digital Technologies, Inc.Inventors: Amit Sharma, Dinesh Kumar Agarwal, Abhinandan Venugopal
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Publication number: 20220391100Abstract: A data storage device and method for efficient image searching are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to store a plurality of images and a plurality of keys in the memory, wherein each key of the plurality of keys is generated from a respective image of the plurality of images; receive, from a host, a key generated from a target image desired by the host; and return, to the host, an image from the stored plurality of images that is associated with a key that matches the key received from the host. Other embodiments are provided.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Applicant: Western Digital Technologies, Inc.Inventors: Amit Sharma, Dinesh Kumar Agarwal, Abhinandan Venugopal