Patents by Inventor Abhinandan Venugopal

Abhinandan Venugopal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960766
    Abstract: A data storage device and method for accidental delete protection are provided. In one embodiment, a data storage device comprises a memory and a controller. The memory comprises a first set of physical blocks and a second set of physical blocks, where the first and second sets of physical blocks are associated with separate logical-to-physical address tables and/or separate block lists. The controller is configured to write data received from a host in the first set of physical blocks and move the data from the first set of physical blocks to the second set of physical blocks in response to the host requesting that a modified version of the data be written in the memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: April 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Abhinandan Venugopal, Amit Sharma
  • Patent number: 11941263
    Abstract: A data storage device having an FTL configured to award to some pending memory operations a higher priority compared to the priority given to those operations by a default scheduling scheme. Such awards of higher priority may be based on a policy directed, e.g., at maximizing the effective data throughput, balancing the data throughput and the input/output bus throughput, or other performance objective. In response to awards of higher priority, a power-management circuit of the data storage device may dynamically route a constrained power supply such that the storage dies corresponding to the higher-priority operations preferentially receive power allocation in the next time interval(s). The remainder of the power budget (if any) in those time intervals may be allocated in accordance with the default scheduling scheme.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: March 26, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Niranjana Bhatta, Abhinandan Venugopal
  • Publication number: 20240094951
    Abstract: A programming order of memory dies of a metablock is typically fixed. However, in some storage architectures, this may cause performance bottlenecks. As such, the programming order of the memory dies may be altered to reduce or eliminate performance bottlenecks.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Amit Sharma, Abhinandan Venugopal
  • Publication number: 20230409234
    Abstract: A data storage device and method are provided for host multi-command queue grouping based on write-size alignment in a multi-queue-depth environment. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to provide a host with an indication of a required amount of data needed to program a set of multi-level cell blocks in the memory; receive an assurance from the host that the host will be providing the data storage device with the required amount of data; and based on the assurance received from the host, program the set of multi-level cell blocks as data is received from the host but before the required amount of data is received from the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: May 17, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Dinesh Kumar Agarwal, Abhinandan Venugopal
  • Publication number: 20230350586
    Abstract: A data storage device having an FTL configured to award to some pending memory operations a higher priority compared to the priority given to those operations by a default scheduling scheme. Such awards of higher priority may be based on a policy directed, e.g., at maximizing the effective data throughput, balancing the data throughput and the input/output bus throughput, or other performance objective. In response to awards of higher priority, a power-management circuit of the data storage device may dynamically route a constrained power supply such that the storage dies corresponding to the higher-priority operations preferentially receive power allocation in the next time interval(s). The remainder of the power budget (if any) in those time intervals may be allocated in accordance with the default scheduling scheme.
    Type: Application
    Filed: May 2, 2022
    Publication date: November 2, 2023
    Inventors: Amit Sharma, Niranjana Bhatta, Abhinandan Venugopal
  • Patent number: 11797387
    Abstract: Example storage systems, storage devices, and methods provide dynamic redundant array of independent disks (RAID) stripe allocation based on memory device health conditions. A device health condition is assigned to each data chunk of a RAID stripe before the data chunk is sent to the target storage device. The write command indicates the device health condition and the receiving storage device selects the storage location for the data chunk corresponding to the device health condition.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 24, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Dinesh Kumar Agarwal, Abhinandan Venugopal
  • Publication number: 20230315335
    Abstract: A data storage device receives a speculative read command from a host identifying logical block addresses. The speculative read command is not required be to executed within a certain amount of time or even at all. The data storage device at least partially executes the speculative read command in response to determining that such execution will not reduce performance of the data storage device. At least partially executing the speculative read command causes data associated with at least some of the logical block addresses to be read from the non-volatile memory and stored in at least one buffer. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Abhinandan Venugopal, Amit Sharma, Anindita Chakrabarty
  • Patent number: 11775191
    Abstract: A data storage device including, in one implementation, a non-volatile memory device including a memory block that includes a plurality of memory dies and a controller that is coupled to the non-volatile memory device and that allocates power to non-memory components based on a determined usage of the memory dies. The controller is configured to monitor a utilization of the plurality of memory dies, determine a utilization state of the plurality of memory dies, and calculate an amount of available power allocated to the plurality of memory dies in response to determining that the plurality of memory dies are in a low utilization state. The controller is also configured to determine whether the amount of available power is above a predetermined threshold, and reallocate the available power to one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: October 3, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Abhinandan Venugopal, Dinesh Kumar Agarwal, Akhilesh Yadav
  • Publication number: 20230176780
    Abstract: A data storage device and method for accidental delete protection are provided. In one embodiment, a data storage device comprises a memory and a controller. The memory comprises a first set of physical blocks and a second set of physical blocks, where the first and second sets of physical blocks are associated with separate logical-to-physical address tables and/or separate block lists. The controller is configured to write data received from a host in the first set of physical blocks and move the data from the first set of physical blocks to the second set of physical blocks in response to the host requesting that a modified version of the data be written in the memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Abhinandan Venugopal, Amit Sharma
  • Patent number: 11586384
    Abstract: The disclosure provides data storage devices, methods, and apparatuses including, among other things, a NAND feature through which software may define logical die groups. Moreover, these logical die groups are indexed and operated with indexed single commands, which is selective-multi-casting to specific dies. In one implementation, a data storage device includes a NAND memory and a controller. The NAND memory including a plurality of dies. The controller is coupled to the NAND memory and configured to generate an index by assigning each die of the plurality of dies to one logical group of a plurality of logical groups, and create the plurality of logical groups in the NAND memory by sending one or more command sequences to the NAND memory that groups the plurality of dies into the plurality of logical groups based on the index that is generated.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: February 21, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Abhinandan Venugopal, Amit Sharma, Vijay Chinchole
  • Patent number: 11573706
    Abstract: A data storage device and method for efficient image searching are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to store a plurality of images and a plurality of keys in the memory, wherein each key of the plurality of keys is generated from a respective image of the plurality of images; receive, from a host, a key generated from a target image desired by the host; and return, to the host, an image from the stored plurality of images that is associated with a key that matches the key received from the host. Other embodiments are provided.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: February 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Dinesh Kumar Agarwal, Abhinandan Venugopal
  • Publication number: 20220391100
    Abstract: A data storage device and method for efficient image searching are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to store a plurality of images and a plurality of keys in the memory, wherein each key of the plurality of keys is generated from a respective image of the plurality of images; receive, from a host, a key generated from a target image desired by the host; and return, to the host, an image from the stored plurality of images that is associated with a key that matches the key received from the host. Other embodiments are provided.
    Type: Application
    Filed: June 7, 2021
    Publication date: December 8, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Dinesh Kumar Agarwal, Abhinandan Venugopal
  • Publication number: 20220291839
    Abstract: A data storage device including, in one implementation, a non-volatile memory device including a memory block that includes a plurality of memory dies and a controller that is coupled to the non-volatile memory device and that allocates power to non-memory components based on a determined usage of the memory dies. The controller is configured to monitor a utilization of the plurality of memory dies, determine a utilization state of the plurality of memory dies, and calculate an amount of available power allocated to the plurality of memory dies in response to determining that the plurality of memory dies are in a low utilization state. The controller is also configured to determine whether the amount of available power is above a predetermined threshold, and reallocate the available power to one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 15, 2022
    Inventors: Amit Sharma, Abhinandan Venugopal, Dinesh Kumar Agarwal, Akhilesh Yadav
  • Publication number: 20220261181
    Abstract: The disclosure provides data storage devices, methods, and apparatuses including, among other things, a NAND feature through which software may define logical die groups. Moreover, these logical die groups are indexed and operated with indexed single commands, which is selective-multi-casting to specific dies. In one implementation, a data storage device includes a NAND memory and a controller. The NAND memory including a plurality of dies. The controller is coupled to the NAND memory and configured to generate an index by assigning each die of the plurality of dies to one logical group of a plurality of logical groups, and create the plurality of logical groups in the NAND memory by sending one or more command sequences to the NAND memory that groups the plurality of dies into the plurality of logical groups based on the index that is generated.
    Type: Application
    Filed: February 16, 2021
    Publication date: August 18, 2022
    Inventors: Abhinandan Venugopal, Amit Sharma, Vijay Chinchole
  • Patent number: 11379137
    Abstract: A data storage device including, in one implementation, a non-volatile memory device including a memory block that includes a plurality of memory dies and a controller that is coupled to the non-volatile memory device and that allocates power to non-memory components based on a determined usage of the memory dies. The controller is configured to monitor a utilization of the plurality of memory dies, determine a utilization state of the plurality of memory dies, and calculate an amount of available power allocated to the plurality of memory dies in response to determining that the plurality of memory dies are in a low utilization state. The controller is also configured to determine whether the amount of available power is above a predetermined threshold, and reallocate the available power to one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: July 5, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Abhinandan Venugopal, Dinesh Kumar Agarwal, Akhilesh Yadav
  • Patent number: 11281405
    Abstract: Aspects of a storage device including a plurality of dies and a controller are provided which allow for asymmetric die operation handling so that controller overheads associated with common resource intensive operations may be incurred in the background without delaying subsequent die operations. When the controller receives a command to perform an MLC operation such as programming a number of dies, the controller refrains from performing the MLC operation in one or more of the dies for a period of time while simultaneously performing the MLC operation in a remainder of the dies. Instead, the controller performs another operation, such as an SLC operation, another MLC operation, or a transfer operation, that involves a common resource in these dies during the period of time. Controller overheads associated with these other operations thus are incurred without creating bottlenecks when the number of dies is large, thereby improving storage device performance.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: March 22, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Amit Sharma, Abhinandan Venugopal, Dinesh Kumar Agarwal
  • Patent number: 11262947
    Abstract: An apparatus includes a plurality of memory die and a controller coupled to the plurality of memory die. The controller is configured to selectively process a plurality of random read commands in such a way to reduce a total time required to execute the random read commands.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: March 1, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Abhinandan Venugopal, Amit Sharma, Dinesh Kumar Agarwal
  • Publication number: 20210397517
    Abstract: Example storage systems, storage devices, and methods provide dynamic redundant array of independent disks (RAID) stripe allocation based on memory device health conditions. A device health condition is assigned to each data chunk of a RAID stripe before the data chunk is sent to the target storage device. The write command indicates the device health condition and the receiving storage device selects the storage location for the data chunk corresponding to the device health condition.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 23, 2021
    Inventors: Amit Sharma, Dinesh Kumar Agarwal, Abhinandan Venugopal
  • Publication number: 20210382818
    Abstract: Disclosed herein is a solid-state storage device that reduces read time for read time-sensitive data (“RTS data”). Data-characterizing logic characterizes incoming data from a host system as primary data including the RTS data or secondary data including non-RTS data. Memory-cell programming schemes include a primary data-programming scheme for a reduced read-frequency zone for the primary data and a secondary data-programming scheme standard read-frequency zone for the secondary data. Data routing logic routes the primary data to a plurality of physical pages corresponding to lower logical pages of a plurality of logical pages in the at-least-one reduced read-frequency zone with assistance by a logical-to-physical address translator. The lower logical pages require fewer read operations than upper logical pages of the plurality of logical pages to read the primary data, which results in a reduction of the read time for the RTS data in the at-least-one reduced read-frequency zone.
    Type: Application
    Filed: June 8, 2020
    Publication date: December 9, 2021
    Inventors: Amit Sharma, Abhinandan Venugopal, Vijay Chinchole
  • Publication number: 20210382652
    Abstract: Aspects of a storage device including a plurality of dies and a controller are provided which allow for asymmetric die operation handling so that controller overheads associated with common resource intensive operations may be incurred in the background without delaying subsequent die operations. When the controller receives a command to perform an MLC operation such as programming a number of dies, the controller refrains from performing the MLC operation in one or more of the dies for a period of time while simultaneously performing the MLC operation in a remainder of the dies. Instead, the controller performs another operation, such as an SLC operation, another MLC operation, or a transfer operation, that involves a common resource in these dies during the period of time. Controller overheads associated with these other operations thus are incurred without creating bottlenecks when the number of dies is large, thereby improving storage device performance.
    Type: Application
    Filed: June 8, 2020
    Publication date: December 9, 2021
    Inventors: Amit Sharma, Abhinandan Venugopal, Dinesh Kumar Agarwal