Patents by Inventor Abhinav GAUR

Abhinav GAUR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240118682
    Abstract: A system includes a memory storing a dimensionally aware model generated based on a training set and guided by feature dimensions and instructions for execution a processor. The instructions include, in response to receiving a set of data from a user device, identifying a set of features from the set of data and applying the dimensionally aware model to the set of features by implementing a boundary representation.
    Type: Application
    Filed: December 14, 2023
    Publication date: April 11, 2024
    Inventors: Abhinav GAUR, Kalyanmoy DEB, Debejyo CHAKRABORTY, Jeffrey A. ABELL
  • Publication number: 20240075614
    Abstract: The system can include a set of joints, a controller, and a model engine; and can optionally include a support structure and an end effector. Joints can include: a motor, a transmission mechanism, an input sensor, and an output sensor. The system can enable articulation of the plurality of joints.
    Type: Application
    Filed: November 10, 2023
    Publication date: March 7, 2024
    Inventors: Abhinav Kumar, Aditya Bhatia, Akash Bansal, Anubhav Singh, Ashutosh Prakash, Aman Malhotra, Harshit Gaur, Prasang Srivasatava, Ashish Chauhan
  • Patent number: 11550681
    Abstract: A system-on-chip includes a memory, an error injection controller, an injection logic circuit, and an error detection circuit. The error injection controller is configured to generate and transmit error data, and at least one of read and write access requests associated with the memory to the injection logic circuit. The injection logic circuit is configured to access the memory based on at least one of the read and write access requests to execute at least one of read and write operations. The injection logic circuit is further configured to inject an error in at least one of first data and second data to generate at least one of erroneous first data and erroneous second data, respectively. The error detection circuit is configured to detect an error in at least one of the erroneous first data and the erroneous second data to generate an error signal.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: January 10, 2023
    Assignee: NXP USA, Inc.
    Inventors: Abhinav Gaur, Neha Bagri
  • Patent number: 11461205
    Abstract: An error management system can include register sets associated with an error reaction. The test errors are injected in functional signals based on activation of multiple bits in one of the register sets. When the functional signals with the injected test errors are received by the error management system, multiple bits in the other register set are activated. The error management system generates an activated indication signal when a number of the activated bits in one register set matches a number of activated bits in the other register set. When the indication signal is activated, the error management system generates a reaction signal indicative of the error reaction. Thus, the error management system generates a single reaction signal in response to the injected test errors requiring the same reaction.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: October 4, 2022
    Assignee: NXP B.V.
    Inventors: Neha Bagri, Abhinav Gaur, Nipun Mahajan
  • Publication number: 20220138066
    Abstract: A system-on-chip includes a memory, an error injection controller, an injection logic circuit, and an error detection circuit. The error injection controller is configured to generate and transmit error data, and at least one of read and write access requests associated with the memory to the injection logic circuit. The injection logic circuit is configured to access the memory based on at least one of the read and write access requests to execute at least one of read and write operations. The injection logic circuit is further configured to inject an error in at least one of first data and second data to generate at least one of erroneous first data and erroneous second data, respectively. The error detection circuit is configured to detect an error in at least one of the erroneous first data and the erroneous second data to generate an error signal.
    Type: Application
    Filed: November 2, 2020
    Publication date: May 5, 2022
    Inventors: Abhinav Gaur, Neha Bagri
  • Publication number: 20210278827
    Abstract: A system includes at least one processor and a memory. The memory stores a dimensionally aware model generated based on a training set and guided by feature dimensions and instructions for execution by the at least one processor. The instructions include, in response to receiving a set of data from a user device, identifying a set of features from the set of data and applying the dimensionally aware model to the set of features by implementing a boundary representation. The instructions include classifying the set of features as acceptable in response to the implementation of the boundary representation indicating the set of features are outside the boundary representation, classifying the set of features as unacceptable in response to the implementation of the boundary representation indicating the set of features are inside the boundary representation, and generating, for display on the user device, an alert based on the classification.
    Type: Application
    Filed: March 8, 2021
    Publication date: September 9, 2021
    Applicants: Board of Trustees of Michigan State University, GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Kalyanmoy DEB, Abhinav GAUR, Debejyo CHAKRABORTY, Jeffrey ABELL