Patents by Inventor Abhinav KARHU

Abhinav KARHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for dynamic control of microprocessor configuration
    Patent number: 11886918
    Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: January 30, 2024
    Assignee: INTEL CORPORATION
    Inventors: Ankush Varma, Nikhil Gupta, Vasudevan Srinivasan, Krishnakanth Sistla, Nilanjan Palit, Abhinav Karhu, Eugene Gorbatov, Eliezer Weissmann
  • APPARATUS AND METHOD FOR DYNAMIC CONTROL OF MICROPROCESSOR CONFIGURATION
    Publication number: 20220244996
    Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.
    Type: Application
    Filed: April 11, 2022
    Publication date: August 4, 2022
    Inventors: Ankush VARMA, Nikhil GUPTA, Vasudevan SRINIVASAN, Krishnakanth SISTLA, Nilanjan PALIT, Abhinav KARHU, Eugene GORBATOV, Eliezer WEISSMANN
  • Apparatus and method for dynamic control of microprocessor configuration
    Patent number: 11301298
    Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors.
    Type: Grant
    Filed: March 28, 2020
    Date of Patent: April 12, 2022
    Assignee: INTEL CORPORATION
    Inventors: Ankush Varma, Nikhil Gupta, Vasudevan Srinivasan, Krishnakanth Sistla, Nilanjan Palit, Abhinav Karhu, Eugene Gorbatov, Eliezer Weissmann
  • Techniques for controlling processor performance states
    Patent number: 11194381
    Abstract: Techniques and apparatus for managing performance states of processing circuitry of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processing circuitry, and logic, at least a portion of comprised in hardware coupled to the at least one processing circuitry, to set a first performance state (P-state) of the at least one processing circuitry based on system utilization information, access a performance interface element comprising a plurality of performance metric hints, update the first P-state to a second P-state responsive to one of the plurality of performance metric hints being set by an operating system (OS) of the apparatus, and maintain the first P-state responsive to none of the plurality of performance metric hints being set by the operating system (OS). Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 7, 2021
    Assignee: INTEL CORPORATION
    Inventors: Abhinav Karhu, Russell Fenger, Vijay Dhanraj, Balaji Masanamuthu Chinnathurai
  • APPARATUS AND METHOD FOR DYNAMIC CONTROL OF MICROPROCESSOR CONFIGURATION
    Publication number: 20210303357
    Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors.
    Type: Application
    Filed: March 28, 2020
    Publication date: September 30, 2021
    Inventors: Ankush VARMA, Nikhil GUPTA, Vasudevan SRINIVASAN, Krishnakanth SISTLA, Nilanjan PALIT, Abhinav KARHU, Eugene GORBATOV, Eliezer WEISSMANN
  • TECHNIQUES FOR CONTROLLING PROCESSOR PERFORMANCE STATES
    Publication number: 20200356156
    Abstract: Techniques and apparatus for managing performance states of processing circuitry of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processing circuitry, and logic, at least a portion of comprised in hardware coupled to the at least one processing circuitry, to set a first performance state (P-state) of the at least one processing circuitry based on system utilization information, access a performance interface element comprising a plurality of performance metric hints, update the first P-state to a second P-state responsive to one of the plurality of performance metric hints being set by an operating system (OS) of the apparatus, and maintain the first P-state responsive to none of the plurality of performance metric hints being set by the operating system (OS). Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: November 12, 2020
    Applicant: INTEL CORPORATION
    Inventors: Abhinav KARHU, Russell FENGER, Vijay DHANRAJ, Balaji MASANAMUTHU CHINNATHURAI