Patents by Inventor Abhinav Tripathi

Abhinav Tripathi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230402389
    Abstract: A memory array including integrated word line (WL) contact structures are disclosed. The memory array comprises a plurality of WLs that includes at least a first WL and a second WL. An integrated WL contact structure includes a first WL contact and a second WL contact for the first WL and the second WL, respectively. The second WL contact extends through the first WL contact. For example, the second WL contact is nested within the first WL contact. An intervening isolation material isolates the second WL contact from the first WL contact. In an example, the second WL contact extends through a hole in the first WL to reach the second WL. The isolation material isolates the second WL contact from sidewalls of the hole in the first WL.
    Type: Application
    Filed: August 18, 2023
    Publication date: December 14, 2023
    Inventors: Nanda Kumar Chakravarthi, Kwame Nkrumah Eason, Abhinav Tripathi, Ebony Lynn MAYS, Jessica Sevanne Kachian, Ralf Buengener
  • Publication number: 20230046838
    Abstract: Disclosed herein is a stabilised Na-ion oxide P3 phase of formula (I): P3-NaxMyOz Where, x>0.66, 0.8?y?1.0, z?2; and M is selected from one or more of the group consisting of a 3d transition metal, a 4d transition metal, Al, Mg, B, Si, Sn, Sr and Ca. The stabilised Na-ion oxide P3 phase of formula (I) may be particularly useful as an active material in a Na-ion battery.
    Type: Application
    Filed: January 21, 2021
    Publication date: February 16, 2023
    Inventors: Balaya PALANI, Abhinav TRIPATHI
  • Publication number: 20220189976
    Abstract: Embodiments of the present disclosure are directed towards a memory device including a top wordline contact located in a region that is protected from erosion during a planarization process, e.g., chemical mechanical polish (CMP). In embodiments, a plurality of wordlines are formed in a stack of multiple layers and a plurality of wordline contacts are formed to intersect with the plurality of wordlines. In embodiments, the stack forms a staircase and each of the plurality of wordline contacts lands on a corresponding each of the wordlines proximate to an edge of the staircase such that a top wordline contact lands in a region on a top wordline previously covered by a sacrificial layer. In some embodiments, the region is proximate to a raised notch at an edge of the staircase. Other embodiments may be described and claimed.
    Type: Application
    Filed: June 10, 2019
    Publication date: June 16, 2022
    Inventors: Nanda Kumar CHAKRAVARTHI, David MEYAARD, Abhinav TRIPATHI, Liu LIU
  • Publication number: 20210143100
    Abstract: A memory array including integrated word line (WL) contact structures are disclosed. The memory array comprises a plurality of WLs that includes at least a first WL and a second WL. An integrated WL contact structure includes a first WL contact and a second WL contact for the first WL and the second WL, respectively. The second WL contact extends through the first WL contact. For example, the second WL contact is nested within the first WL contact. An intervening isolation material isolates the second WL contact from the first WL contact. In an example, the second WL contact extends through a hole in the first WL to reach the second WL. The isolation material isolates the second WL contact from sidewalls of the hole in the first WL.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 13, 2021
    Applicant: Intel Corporation
    Inventors: Nanda Kumar Chakravarthi, Kwame Nkrumah Eason, Abhinav Tripathi, Ebony Lynn Mays, Jessica Sevanne Kachian, Ralf Buengener
  • Publication number: 20080142375
    Abstract: Compositions and methods suitable for the electrochemical mechanical planarization of a conductive material layer on a semiconductor workpiece. Compositions contain a phosphonic acid based electrolyte, a corrosion inhibitor, a chelating agent, a pH adjusting agent, and a solvent as the remainder.
    Type: Application
    Filed: September 28, 2007
    Publication date: June 19, 2008
    Inventors: Francois Doniat, Matthew L. Fisher, Alan D. Zdunek, Alexandro A. Barajas, Ian Suni, Xiangfeng Chu, Abhinav Tripathi, Yuzhuo Li